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Merge branch 'pci/enumeration'
- Remove MPS/MRRS Kconfig settings (CONFIG_PCIE_BUS_*) that worked around a WiFi device defect (Bjorn Helgaas) - Always lift 2.5GT/s restriction in PCIe failed link retraining to avoid clamping a link to 2.5GT/s after hot-plug changes the device (Maciej W. Rozycki) - Don't bother trying to retrain a 2.5GT/s link at 2.5GT/s since nothing would be gained by the retrain (Maciej W. Rozycki) * pci/enumeration: PCI: Bail out early for 2.5GT/s devices in PCIe failed link retraining PCI: Use pcie_get_speed_cap() in PCIe failed link retraining PCI: Always lift 2.5GT/s restriction in PCIe failed link retraining PCI: Remove MPS/MRRS Kconfig settings (CONFIG_PCIE_BUS_*)
This commit is contained in:
Bjorn Helgaas
commit
1eaa2b8d4c
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@ -251,63 +251,6 @@ config PCI_DYNAMIC_OF_NODES
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Once this option is selected, the device tree nodes will be generated
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for all PCI bridges.
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choice
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prompt "PCI Express hierarchy optimization setting"
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default PCIE_BUS_DEFAULT
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depends on EXPERT
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help
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MPS (Max Payload Size) and MRRS (Max Read Request Size) are PCIe
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device parameters that affect performance and the ability to
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support hotplug and peer-to-peer DMA.
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The following choices set the MPS and MRRS optimization strategy
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at compile-time. The choices are the same as those offered for
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the kernel command-line parameter 'pci', i.e.,
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'pci=pcie_bus_tune_off', 'pci=pcie_bus_safe',
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'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'.
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This is a compile-time setting and can be overridden by the above
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command-line parameters. If unsure, choose PCIE_BUS_DEFAULT.
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config PCIE_BUS_TUNE_OFF
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bool "Tune Off"
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help
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Use the BIOS defaults; don't touch MPS at all. This is the same
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as booting with 'pci=pcie_bus_tune_off'.
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config PCIE_BUS_DEFAULT
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bool "Default"
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help
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Default choice; ensure that the MPS matches upstream bridge.
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config PCIE_BUS_SAFE
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bool "Safe"
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help
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Use largest MPS that boot-time devices support. If you have a
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closed system with no possibility of adding new devices, this
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will use the largest MPS that's supported by all devices. This
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is the same as booting with 'pci=pcie_bus_safe'.
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config PCIE_BUS_PERFORMANCE
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bool "Performance"
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help
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Use MPS and MRRS for best performance. Ensure that a given
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device's MPS is no larger than its parent MPS, which allows us to
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keep all switches/bridges to the max MPS supported by their
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parent. This is the same as booting with 'pci=pcie_bus_perf'.
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config PCIE_BUS_PEER2PEER
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bool "Peer2peer"
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help
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Set MPS = 128 for all devices. MPS configuration effected by the
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other options could cause the MPS on one root port to be
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different than that of the MPS on another, which may cause
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hot-added devices or peer-to-peer DMA to fail. Set MPS to the
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smallest possible value (128B) system-wide to avoid these issues.
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This is the same as booting with 'pci=pcie_bus_peer2peer'.
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endchoice
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config VGA_ARB
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bool "VGA Arbitration" if EXPERT
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default y
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@ -120,17 +120,7 @@ unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
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/* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
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#ifdef CONFIG_PCIE_BUS_TUNE_OFF
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
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#elif defined CONFIG_PCIE_BUS_SAFE
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
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#elif defined CONFIG_PCIE_BUS_PERFORMANCE
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
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#elif defined CONFIG_PCIE_BUS_PEER2PEER
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
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#else
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
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#endif
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/*
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* The default CLS is used if arch didn't set CLS explicitly and not
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@ -80,11 +80,10 @@ static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta)
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* Restrict the speed to 2.5GT/s then with the Target Link Speed field,
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* request a retrain and check the result.
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*
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* If this turns out successful and we know by the Vendor:Device ID it is
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* safe to do so, then lift the restriction, letting the devices negotiate
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* a higher speed. Also check for a similar 2.5GT/s speed restriction the
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* firmware may have already arranged and lift it with ports that already
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* report their data link being up.
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* If this turns out successful, or where a 2.5GT/s speed restriction has
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* been previously arranged by the firmware and the port reports its link
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* already being up, lift the restriction, in a hope it is safe to do so,
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* letting the devices negotiate a higher speed.
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*
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* Otherwise revert the speed to the original setting and request a retrain
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* again to remove any residual state, ignoring the result as it's supposed
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@ -95,51 +94,39 @@ static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta)
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*/
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int pcie_failed_link_retrain(struct pci_dev *dev)
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{
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static const struct pci_device_id ids[] = {
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{ PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */
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{}
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};
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u16 lnksta, lnkctl2;
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u16 lnksta, lnkctl2, oldlnkctl2;
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enum pci_bus_speed speed_cap;
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int ret = -ENOTTY;
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if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) ||
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!pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
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return ret;
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speed_cap = pcie_get_speed_cap(dev);
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if (speed_cap <= PCIE_SPEED_2_5GT)
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return ret;
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
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pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2);
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if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) {
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u16 oldlnkctl2;
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pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
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pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2);
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ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false);
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if (ret) {
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pci_info(dev, "retraining failed\n");
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pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2),
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true);
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return ret;
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}
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
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if (ret)
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goto err;
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}
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pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
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if ((lnksta & PCI_EXP_LNKSTA_DLLLA) &&
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(lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT &&
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pci_match_id(ids, dev)) {
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u32 lnkcap;
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if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT) {
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pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
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pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
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ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false);
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if (ret) {
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pci_info(dev, "retraining failed\n");
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return ret;
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}
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ret = pcie_set_target_speed(dev, speed_cap, false);
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if (ret)
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goto err;
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}
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return ret;
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err:
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pci_info(dev, "retraining failed\n");
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pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), true);
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return ret;
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}
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