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dt-bindings: pinctrl: describe the Qualcomm nord-tlmm
Add a DT binding document describing the TLMM pin controller available on the Nord platforms from Qualcomm. Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Bartosz Golaszewski
Linus Walleij
parent
334f7bcbdc
commit
1ea146943d
141
Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml
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141
Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SA8797P TLMM block
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maintainers:
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- Bartosz Golaszewski <brgl@kernel.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,nord-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 90
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gpio-line-names:
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maxItems: 181
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-nord-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-nord-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-nord-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$"
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- enum: [ ufs_reset ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,
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aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,
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aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,
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aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,
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aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,
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aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,
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aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,
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aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,
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aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,
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aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,
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aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,
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aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,
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aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,
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aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,
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bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,
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clink_debug, dbg_out, dbg_out_clk,
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ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
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ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,
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dp_rx11, dp_rx1_mute,
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edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,
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edp3_hot, edp3_lcd,
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emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,
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emac1_mdc, emac1_mdio, emac1_ptp,
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gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,
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gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,
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mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,
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mdp_vsync_p, mdp_vsync_s,
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pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,
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pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
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prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,
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qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
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qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,
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qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
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qup2_se5, qup2_se6,
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sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,
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smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,
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tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,
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usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,
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usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,nord-tlmm";
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reg = <0x0f100000 0xc0000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 181>;
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wakeup-parent = <&pdc>;
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qup_uart15_default: qup-uart15-default-state {
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pins = "gpio147", "gpio148";
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function = "qup2_se2";
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drive-strength = <2>;
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bias-disable;
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};
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};
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...
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