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pinctrl: qcom: shikra: Fix intr_target_width for summary interrupt routing

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The intr_target_width field sets the mask width used when writing
target processor into interrupt config register and deciding which
processor receives summary interrupt for a given GPIO.

Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this
field is 4 bits wide, which could corrupt adjacent bits and mis-route
interrupts. Set intr_target_width = 4 to match the hardware.

Fixes: 9db68ec534 ("pinctrl: qcom: Add Shikra pinctrl driver")
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
This commit is contained in:
Komal Bajaj 2026-07-28 16:33:08 +05:30 committed by Bartosz Golaszewski
parent fd46760956
commit 1e7b04c12c
1 changed files with 1 additions and 0 deletions
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1
drivers/pinctrl/qcom/pinctrl-shikra.c
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@ -44,6 +44,7 @@
.intr_status_bit = 0, \
.intr_wakeup_enable_bit = 7, \
.intr_wakeup_present_bit = 6, \
.intr_target_width = 4, \
.intr_target_bit = 8, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \