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arm64: dts: exynos: Add initial support for the Exynos 990 SoC

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The Exynos 990 SoC is an ARMv8 mobile SoC found in Samsung Galaxy N/S20
series phones (x1sxxx, c1sxxx). Add minimal support for this SoC,
including:

- All 8 cores via PSCI
- ChipID
- Generic timer.
- Pinctrl

The devices using this SoC suffer from the same issue as Exynos 8895
caused by the stock Samsung bootloader, as it doesn't configure
CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the
timer node, otherwise the kernel panics.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20241016154747.64343-6-igor.belwon@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Igor Belwon 2024-10-16 17:47:46 +02:00 committed by Krzysztof Kozlowski
parent f7aeff28f2
commit 1e5f14efd6
2 changed files with 2446 additions and 0 deletions
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arch/arm64/boot/dts/exynos/exynos990-pinctrl.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
* Samsung Exynos 990 SoC device tree source
*
* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "samsung,exynos990";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_cmgp;
pinctrl2 = &pinctrl_hsi1;
pinctrl3 = &pinctrl_hsi2;
pinctrl4 = &pinctrl_peric0;
pinctrl5 = &pinctrl_peric1;
pinctrl6 = &pinctrl_vts;
};
arm-a55-pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
arm-a76-pmu {
compatible = "arm,cortex-a76-pmu";
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>,
<&cpu5>;
};
/* There's no PMU model for cluster2, which are the Mongoose cores. */
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
};
cluster2 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x4>;
enable-method = "psci";
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x5>;
enable-method = "psci";
};
cpu6: cpu@200 {
device_type = "cpu";
compatible = "samsung,mongoose-m5";
reg = <0x6>;
enable-method = "psci";
};
cpu7: cpu@201 {
device_type = "cpu";
compatible = "samsung,mongoose-m5";
reg = <0x7>;
enable-method = "psci";
};
};
oscclk: clock-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "oscclk";
};
psci {
compatible = "arm,psci-0.2";
method = "hvc";
};
soc: soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x20000000>;
#address-cells = <1>;
#size-cells = <1>;
chipid@10000000 {
compatible = "samsung,exynos990-chipid",
"samsung,exynos850-chipid";
reg = <0x10000000 0x100>;
};
gic: interrupt-controller@10101000 {
compatible = "arm,gic-400";
reg = <0x10101000 0x1000>,
<0x10102000 0x1000>,
<0x10104000 0x2000>,
<0x10106000 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_HIGH)>;
#address-cells = <0>;
#size-cells = <1>;
};
pinctrl_peric0: pinctrl@10430000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x10430000 0x1000>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_peric1: pinctrl@10730000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x10730000 0x1000>;
interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_hsi1: pinctrl@13040000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x13040000 0x1000>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_hsi2: pinctrl@13c30000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x13c30000 0x1000>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_vts: pinctrl@15580000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x15580000 0x1000>;
};
pinctrl_alive: pinctrl@15850000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x15850000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos990-wakeup-eint",
"samsung,exynos850-wakeup-eint",
"samsung,exynos7-wakeup-eint";
};
};
pinctrl_cmgp: pinctrl@15c30000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x15c30000 0x1000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
/*
* Non-updatable, broken stock Samsung bootloader does not
* configure CNTFRQ_EL0
*/
clock-frequency = <26000000>;
};
};
#include "exynos990-pinctrl.dtsi"