drm/amdgpu: In GFX12.1 CU is same as WGP

Fix this for current ip discovery table.

v2: Move the change to gfx12 file
v3: Change only for the current version of ip discovery table
v4: Squash in build fixes

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harish Kasiviswanathan 2026-02-26 10:34:55 -05:00 committed by Alex Deucher
parent 79ce2a0ced
commit 1e5d97a5c5
3 changed files with 37 additions and 0 deletions

View File

@ -3422,3 +3422,28 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
return 0;
}
int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
uint16_t *major, uint16_t *minor)
{
uint8_t *discovery_bin = adev->discovery.bin;
struct table_info *info;
union gc_info *gc_info;
u16 offset;
if (!discovery_bin)
return -EINVAL;
if (amdgpu_discovery_get_table_info(adev, &info, GC))
return -EINVAL;
offset = le16_to_cpu(info->offset);
if (!offset)
return -EINVAL;
gc_info = (union gc_info *)(discovery_bin + offset);
if (major)
*major = le16_to_cpu(gc_info->v1.header.version_major);
if (minor)
*minor = le16_to_cpu(gc_info->v1.header.version_minor);
return 0;
}

View File

@ -48,6 +48,8 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
uint32_t *nps_type,
struct amdgpu_gmc_memrange *ranges,
int *range_cnt, bool refresh);
int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
uint16_t *major, uint16_t *minor);
void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p);

View File

@ -1142,6 +1142,7 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
{
uint16_t major_ver, minor_ver;
int i, j, k, r, ring_id = 0;
unsigned num_compute_rings;
int xcc_id, num_xcc;
@ -1152,6 +1153,15 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 8;
if (!amdgpu_discovery_get_gc_major_minor_version(
adev, &major_ver, &minor_ver)) {
if (major_ver == 1 && minor_ver == 3) {
adev->gfx.config.max_cu_per_sh /= 2;
dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n",
adev->gfx.config.max_cu_per_sh);
}
}
break;
default:
adev->gfx.mec.num_mec = 2;