diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
deleted file mode 100644
index e41490e6979c..000000000000
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* TI - MPU (Main Processor Unit) subsystem
-
-The MPU subsystem contain one or several ARM cores
-depending of the version.
-The MPU contain CPUs, GIC, L2 cache and a local PRCM.
-
-Required properties:
-- compatible : Should be "ti,omap3-mpu" for OMAP3
-               Should be "ti,omap4-mpu" for OMAP4
-	       Should be "ti,omap5-mpu" for OMAP5
-- ti,hwmods: "mpu"
-
-Optional properties:
-- sram:	Phandle to the ocmcram node
-
-am335x and am437x only:
-- pm-sram: Phandles to ocmcram nodes to be used for power management.
-	   First should be type 'protect-exec' for the driver to use to copy
-	   and run PM functions, second should be regular pool to be used for
-	   data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
-	   for more details.
-
-Examples:
-
-- For an OMAP5 SMP system:
-
-mpu {
-    compatible = "ti,omap5-mpu";
-    ti,hwmods = "mpu"
-};
-
-- For an OMAP4 SMP system:
-
-mpu {
-    compatible = "ti,omap4-mpu";
-    ti,hwmods = "mpu";
-};
-
-
-- For an OMAP3 monocore system:
-
-mpu {
-    compatible = "ti,omap3-mpu";
-    ti,hwmods = "mpu";
-};
-
-- For an AM335x system:
-
-mpu {
-	compatible = "ti,omap3-mpu";
-	ti,hwmods = "mpu";
-	pm-sram = <&pm_sram_code
-		   &pm_sram_data>;
-};
diff --git a/Documentation/devicetree/bindings/arm/ti/ti,omap-mpu.yaml b/Documentation/devicetree/bindings/arm/ti/ti,omap-mpu.yaml
new file mode 100644
index 000000000000..abd8c64e8e9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ti/ti,omap-mpu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/ti/ti,omap-mpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI MPU (Main Processor Unit) subsystem
+
+maintainers:
+  - Benoit Cousson <b-cousson@ti.com>
+
+description:
+  The MPU subsystem contains one or several ARM cores depending on the version.
+  The MPU contains CPUs, GIC, L2 cache and a local PRCM.
+
+properties:
+  compatible:
+    enum:
+      - ti,omap3-mpu
+      - ti,omap4-mpu
+      - ti,omap5-mpu
+
+  ti,hwmods:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: Name of the hwmod associated with the MPU
+    const: mpu
+    deprecated: true
+
+  sram:
+    description: ocmcram node
+
+  pm-sram:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: ocmcram nodes for power management. For am335x and am437x.
+    items:
+      - items:
+          - description: ocmcram node of type protect-exec for PM functions
+      - items:
+          - description: ocmcram node of regular pool to be used for data region
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    mpu {
+        compatible = "ti,omap5-mpu";
+        ti,hwmods = "mpu";
+    };
+
+  - |
+    mpu {
+        compatible = "ti,omap3-mpu";
+        ti,hwmods = "mpu";
+        pm-sram = <&pm_sram_code &pm_sram_data>;
+    };