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net/mlx5: Add IFC bit for TIR/SQ order capability

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Before this cap, firmware requested a certain creation order between TIR
objects and SQs of the same transport domain to properly support the
self loopback prevention feature. If order is not preserved, explicit
modify_tir operations are necessary after the opening of the SQs.

When set, this cap bit indicates that this firmware requirement /
limitation no longer holds.

Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1758521191-814350-2-git-send-email-tariqt@nvidia.com
Reviewed-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Tariq Toukan 2025-09-22 09:06:30 +03:00 committed by Leon Romanovsky
parent a3d076b056
commit 1ddf1636e0
1 changed files with 2 additions and 1 deletions
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3
include/linux/mlx5/mlx5_ifc.h
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@ -1895,7 +1895,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_2a0[0x7];
u8 mkey_pcie_tph[0x1];
u8 reserved_at_2a8[0x2];
u8 reserved_at_2a8[0x1];
u8 tis_tir_td_order[0x1];
u8 psp[0x1];
u8 shampo[0x1];