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tty: serial: fsl_lpuart: rename register variables more specifically
There are many fuzzy register variables in the lpuart driver, such as temp, tmp, val, reg. Let's give these register variables more specific names. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Link: https://lore.kernel.org/r/20250312023904.1343351-4-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sherry Sun
Greg Kroah-Hartman
parent
3cc16ae096
commit
1d9ac5bd4e
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@ -441,36 +441,36 @@ static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
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static void lpuart_stop_tx(struct uart_port *port)
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{
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u8 temp;
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u8 cr2;
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temp = readb(port->membase + UARTCR2);
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temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
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writeb(temp, port->membase + UARTCR2);
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cr2 = readb(port->membase + UARTCR2);
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cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE);
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writeb(cr2, port->membase + UARTCR2);
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}
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static void lpuart32_stop_tx(struct uart_port *port)
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{
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u32 temp;
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u32 ctrl;
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temp = lpuart32_read(port, UARTCTRL);
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temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
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lpuart32_write(port, temp, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
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lpuart32_write(port, ctrl, UARTCTRL);
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}
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static void lpuart_stop_rx(struct uart_port *port)
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{
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u8 temp;
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u8 cr2;
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temp = readb(port->membase + UARTCR2);
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writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
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cr2 = readb(port->membase + UARTCR2);
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writeb(cr2 & ~UARTCR2_RE, port->membase + UARTCR2);
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}
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static void lpuart32_stop_rx(struct uart_port *port)
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{
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u32 temp;
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u32 ctrl;
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temp = lpuart32_read(port, UARTCTRL);
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lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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lpuart32_write(port, ctrl & ~UARTCTRL_RE, UARTCTRL);
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}
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static void lpuart_dma_tx(struct lpuart_port *sport)
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@ -599,7 +599,7 @@ static void lpuart_flush_buffer(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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struct dma_chan *chan = sport->dma_tx_chan;
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u32 val;
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u32 fifo;
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if (sport->lpuart_dma_tx_use) {
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if (sport->dma_tx_in_progress) {
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@ -611,13 +611,13 @@ static void lpuart_flush_buffer(struct uart_port *port)
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}
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if (lpuart_is_32(sport)) {
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val = lpuart32_read(port, UARTFIFO);
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val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
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lpuart32_write(port, val, UARTFIFO);
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fifo = lpuart32_read(port, UARTFIFO);
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fifo |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
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lpuart32_write(port, fifo, UARTFIFO);
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} else {
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val = readb(port->membase + UARTCFIFO);
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val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
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writeb(val, port->membase + UARTCFIFO);
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fifo = readb(port->membase + UARTCFIFO);
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fifo |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
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writeb(fifo, port->membase + UARTCFIFO);
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}
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}
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@ -642,7 +642,7 @@ static int lpuart_poll_init(struct uart_port *port)
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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unsigned long flags;
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u8 temp;
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u8 fifo;
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port->fifosize = 0;
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@ -650,9 +650,9 @@ static int lpuart_poll_init(struct uart_port *port)
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/* Disable Rx & Tx */
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writeb(0, port->membase + UARTCR2);
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temp = readb(port->membase + UARTPFIFO);
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fifo = readb(port->membase + UARTPFIFO);
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/* Enable Rx and Tx FIFO */
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writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
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writeb(fifo | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
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port->membase + UARTPFIFO);
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/* flush Tx and Rx FIFO */
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@ -694,7 +694,7 @@ static int lpuart32_poll_init(struct uart_port *port)
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{
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unsigned long flags;
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u32 temp;
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u32 fifo;
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port->fifosize = 0;
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@ -703,10 +703,10 @@ static int lpuart32_poll_init(struct uart_port *port)
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/* Disable Rx & Tx */
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lpuart32_write(port, 0, UARTCTRL);
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temp = lpuart32_read(port, UARTFIFO);
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fifo = lpuart32_read(port, UARTFIFO);
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/* Enable Rx and Tx FIFO */
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lpuart32_write(port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
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lpuart32_write(port, fifo | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
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/* flush Tx and Rx FIFO */
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lpuart32_write(port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
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@ -789,10 +789,10 @@ static void lpuart_start_tx(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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u8 temp;
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u8 cr2;
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temp = readb(port->membase + UARTCR2);
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writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
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cr2 = readb(port->membase + UARTCR2);
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writeb(cr2 | UARTCR2_TIE, port->membase + UARTCR2);
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if (sport->lpuart_dma_tx_use) {
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if (!lpuart_stopped_or_empty(port))
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@ -806,14 +806,14 @@ static void lpuart_start_tx(struct uart_port *port)
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static void lpuart32_start_tx(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u32 temp;
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u32 ctrl;
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if (sport->lpuart_dma_tx_use) {
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if (!lpuart_stopped_or_empty(port))
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lpuart_dma_tx(sport);
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} else {
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temp = lpuart32_read(port, UARTCTRL);
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lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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lpuart32_write(port, ctrl | UARTCTRL_TIE, UARTCTRL);
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if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
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lpuart32_transmit_buffer(sport);
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@ -1411,9 +1411,9 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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dma_async_issue_pending(chan);
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if (lpuart_is_32(sport)) {
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u32 temp = lpuart32_read(&sport->port, UARTBAUD);
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u32 baud = lpuart32_read(&sport->port, UARTBAUD);
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lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
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lpuart32_write(&sport->port, baud | UARTBAUD_RDMAE, UARTBAUD);
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if (sport->dma_idle_int) {
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u32 ctrl = lpuart32_read(&sport->port, UARTCTRL);
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@ -1520,10 +1520,10 @@ static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termio
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static unsigned int lpuart_get_mctrl(struct uart_port *port)
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{
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unsigned int mctrl = 0;
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u8 reg;
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u8 cr1;
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reg = readb(port->membase + UARTCR1);
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if (reg & UARTCR1_LOOPS)
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cr1 = readb(port->membase + UARTCR1);
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if (cr1 & UARTCR1_LOOPS)
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mctrl |= TIOCM_LOOP;
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return mctrl;
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@ -1532,10 +1532,10 @@ static unsigned int lpuart_get_mctrl(struct uart_port *port)
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static unsigned int lpuart32_get_mctrl(struct uart_port *port)
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{
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unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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u32 reg;
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u32 ctrl;
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reg = lpuart32_read(port, UARTCTRL);
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if (reg & UARTCTRL_LOOPS)
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ctrl = lpuart32_read(port, UARTCTRL);
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if (ctrl & UARTCTRL_LOOPS)
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mctrl |= TIOCM_LOOP;
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return mctrl;
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@ -1543,49 +1543,49 @@ static unsigned int lpuart32_get_mctrl(struct uart_port *port)
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static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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u8 reg;
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u8 cr1;
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reg = readb(port->membase + UARTCR1);
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cr1 = readb(port->membase + UARTCR1);
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/* for internal loopback we need LOOPS=1 and RSRC=0 */
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reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
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cr1 &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
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if (mctrl & TIOCM_LOOP)
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reg |= UARTCR1_LOOPS;
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cr1 |= UARTCR1_LOOPS;
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writeb(reg, port->membase + UARTCR1);
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writeb(cr1, port->membase + UARTCR1);
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}
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static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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u32 reg;
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u32 ctrl;
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reg = lpuart32_read(port, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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/* for internal loopback we need LOOPS=1 and RSRC=0 */
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reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
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ctrl &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
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if (mctrl & TIOCM_LOOP)
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reg |= UARTCTRL_LOOPS;
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ctrl |= UARTCTRL_LOOPS;
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lpuart32_write(port, reg, UARTCTRL);
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lpuart32_write(port, ctrl, UARTCTRL);
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}
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static void lpuart_break_ctl(struct uart_port *port, int break_state)
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{
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u8 temp;
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u8 cr2;
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temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
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cr2 = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
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if (break_state != 0)
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temp |= UARTCR2_SBK;
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cr2 |= UARTCR2_SBK;
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writeb(temp, port->membase + UARTCR2);
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writeb(cr2, port->membase + UARTCR2);
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}
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static void lpuart32_break_ctl(struct uart_port *port, int break_state)
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{
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u32 temp;
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u32 ctrl;
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temp = lpuart32_read(port, UARTCTRL);
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ctrl = lpuart32_read(port, UARTCTRL);
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/*
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* LPUART IP now has two known bugs, one is CTS has higher priority than the
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@ -1602,22 +1602,22 @@ static void lpuart32_break_ctl(struct uart_port *port, int break_state)
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* Disable the transmitter to prevent any data from being sent out
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* during break, then invert the TX line to send break.
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*/
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temp &= ~UARTCTRL_TE;
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lpuart32_write(port, temp, UARTCTRL);
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temp |= UARTCTRL_TXINV;
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lpuart32_write(port, temp, UARTCTRL);
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ctrl &= ~UARTCTRL_TE;
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lpuart32_write(port, ctrl, UARTCTRL);
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ctrl |= UARTCTRL_TXINV;
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lpuart32_write(port, ctrl, UARTCTRL);
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} else {
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/* Disable the TXINV to turn off break and re-enable transmitter. */
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temp &= ~UARTCTRL_TXINV;
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lpuart32_write(port, temp, UARTCTRL);
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temp |= UARTCTRL_TE;
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lpuart32_write(port, temp, UARTCTRL);
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ctrl &= ~UARTCTRL_TXINV;
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lpuart32_write(port, ctrl, UARTCTRL);
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ctrl |= UARTCTRL_TE;
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lpuart32_write(port, ctrl, UARTCTRL);
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}
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}
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static void lpuart_setup_watermark(struct lpuart_port *sport)
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{
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u8 val, cr2, cr2_saved;
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u8 fifo, cr2, cr2_saved;
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cr2 = readb(sport->port.membase + UARTCR2);
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cr2_saved = cr2;
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@ -1625,8 +1625,8 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
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UARTCR2_RIE | UARTCR2_RE);
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writeb(cr2, sport->port.membase + UARTCR2);
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val = readb(sport->port.membase + UARTPFIFO);
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writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
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fifo = readb(sport->port.membase + UARTPFIFO);
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writeb(fifo | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
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sport->port.membase + UARTPFIFO);
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/* flush Tx and Rx FIFO */
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@ -1696,14 +1696,14 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport)
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static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
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{
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u32 temp;
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u32 ctrl;
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lpuart32_setup_watermark(sport);
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temp = lpuart32_read(&sport->port, UARTCTRL);
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temp |= UARTCTRL_RE | UARTCTRL_TE;
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temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
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lpuart32_write(&sport->port, temp, UARTCTRL);
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ctrl = lpuart32_read(&sport->port, UARTCTRL);
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ctrl |= UARTCTRL_RE | UARTCTRL_TE;
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ctrl |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
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lpuart32_write(&sport->port, ctrl, UARTCTRL);
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}
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static void rx_dma_timer_init(struct lpuart_port *sport)
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@ -1820,16 +1820,16 @@ static void lpuart_hw_setup(struct lpuart_port *sport)
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static int lpuart_startup(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u8 temp;
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u8 fifo;
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/* determine FIFO size and enable FIFO mode */
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temp = readb(port->membase + UARTPFIFO);
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fifo = readb(port->membase + UARTPFIFO);
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sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
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sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_TXSIZE_OFF) &
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UARTPFIFO_FIFOSIZE_MASK);
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port->fifosize = sport->txfifo_size;
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sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
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sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTPFIFO_RXSIZE_OFF) &
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UARTPFIFO_FIFOSIZE_MASK);
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lpuart_request_dma(sport);
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@ -1840,24 +1840,24 @@ static int lpuart_startup(struct uart_port *port)
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static void lpuart32_hw_disable(struct lpuart_port *sport)
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{
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u32 temp;
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u32 ctrl;
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temp = lpuart32_read(&sport->port, UARTCTRL);
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temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
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ctrl = lpuart32_read(&sport->port, UARTCTRL);
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ctrl &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
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UARTCTRL_TIE | UARTCTRL_TE);
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lpuart32_write(&sport->port, temp, UARTCTRL);
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lpuart32_write(&sport->port, ctrl, UARTCTRL);
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}
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static void lpuart32_configure(struct lpuart_port *sport)
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{
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u32 temp;
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u32 ctrl;
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temp = lpuart32_read(&sport->port, UARTCTRL);
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ctrl = lpuart32_read(&sport->port, UARTCTRL);
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if (!sport->lpuart_dma_rx_use)
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temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
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ctrl |= UARTCTRL_RIE | UARTCTRL_ILIE;
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if (!sport->lpuart_dma_tx_use)
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temp |= UARTCTRL_TIE;
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lpuart32_write(&sport->port, temp, UARTCTRL);
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ctrl |= UARTCTRL_TIE;
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lpuart32_write(&sport->port, ctrl, UARTCTRL);
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}
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static void lpuart32_hw_setup(struct lpuart_port *sport)
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@ -1880,16 +1880,16 @@ static void lpuart32_hw_setup(struct lpuart_port *sport)
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static int lpuart32_startup(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u32 temp;
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u32 fifo;
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/* determine FIFO size */
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temp = lpuart32_read(port, UARTFIFO);
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fifo = lpuart32_read(port, UARTFIFO);
|
||||
|
||||
sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
|
||||
sport->txfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_TXSIZE_OFF) &
|
||||
UARTFIFO_FIFOSIZE_MASK);
|
||||
port->fifosize = sport->txfifo_size;
|
||||
|
||||
sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
|
||||
sport->rxfifo_size = UARTFIFO_DEPTH((fifo >> UARTFIFO_RXSIZE_OFF) &
|
||||
UARTFIFO_FIFOSIZE_MASK);
|
||||
|
||||
/*
|
||||
|
|
@ -1934,16 +1934,16 @@ static void lpuart_dma_shutdown(struct lpuart_port *sport)
|
|||
static void lpuart_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
|
||||
u8 temp;
|
||||
u8 cr2;
|
||||
unsigned long flags;
|
||||
|
||||
uart_port_lock_irqsave(port, &flags);
|
||||
|
||||
/* disable Rx/Tx and interrupts */
|
||||
temp = readb(port->membase + UARTCR2);
|
||||
temp &= ~(UARTCR2_TE | UARTCR2_RE |
|
||||
cr2 = readb(port->membase + UARTCR2);
|
||||
cr2 &= ~(UARTCR2_TE | UARTCR2_RE |
|
||||
UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
|
||||
writeb(temp, port->membase + UARTCR2);
|
||||
writeb(cr2, port->membase + UARTCR2);
|
||||
|
||||
uart_port_unlock_irqrestore(port, flags);
|
||||
|
||||
|
|
@ -2141,7 +2141,7 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
|
|||
unsigned int baudrate, bool use_rx_dma,
|
||||
bool use_tx_dma)
|
||||
{
|
||||
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
|
||||
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, baud;
|
||||
u32 clk = port->uartclk;
|
||||
|
||||
/*
|
||||
|
|
@ -2170,9 +2170,9 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
|
|||
tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
|
||||
|
||||
/* select best values between sbr and sbr+1 */
|
||||
tmp = clk / (tmp_osr * (tmp_sbr + 1));
|
||||
if (tmp_diff > (baudrate - tmp)) {
|
||||
tmp_diff = baudrate - tmp;
|
||||
baud = clk / (tmp_osr * (tmp_sbr + 1));
|
||||
if (tmp_diff > (baudrate - baud)) {
|
||||
tmp_diff = baudrate - baud;
|
||||
tmp_sbr++;
|
||||
}
|
||||
|
||||
|
|
@ -2194,23 +2194,23 @@ static void __lpuart32_serial_setbrg(struct uart_port *port,
|
|||
dev_warn(port->dev,
|
||||
"unacceptable baud rate difference of more than 3%%\n");
|
||||
|
||||
tmp = lpuart32_read(port, UARTBAUD);
|
||||
baud = lpuart32_read(port, UARTBAUD);
|
||||
|
||||
if ((osr > 3) && (osr < 8))
|
||||
tmp |= UARTBAUD_BOTHEDGE;
|
||||
baud |= UARTBAUD_BOTHEDGE;
|
||||
|
||||
tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
|
||||
tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
|
||||
baud &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
|
||||
baud |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
|
||||
|
||||
tmp &= ~UARTBAUD_SBR_MASK;
|
||||
tmp |= sbr & UARTBAUD_SBR_MASK;
|
||||
baud &= ~UARTBAUD_SBR_MASK;
|
||||
baud |= sbr & UARTBAUD_SBR_MASK;
|
||||
|
||||
if (!use_rx_dma)
|
||||
tmp &= ~UARTBAUD_RDMAE;
|
||||
baud &= ~UARTBAUD_RDMAE;
|
||||
if (!use_tx_dma)
|
||||
tmp &= ~UARTBAUD_TDMAE;
|
||||
baud &= ~UARTBAUD_TDMAE;
|
||||
|
||||
lpuart32_write(port, tmp, UARTBAUD);
|
||||
lpuart32_write(port, baud, UARTBAUD);
|
||||
}
|
||||
|
||||
static void lpuart32_serial_setbrg(struct lpuart_port *sport,
|
||||
|
|
@ -3085,7 +3085,7 @@ static int lpuart_suspend_noirq(struct device *dev)
|
|||
static int lpuart_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct lpuart_port *sport = dev_get_drvdata(dev);
|
||||
u32 val;
|
||||
u32 stat;
|
||||
|
||||
pinctrl_pm_select_default_state(dev);
|
||||
|
||||
|
|
@ -3094,8 +3094,8 @@ static int lpuart_resume_noirq(struct device *dev)
|
|||
|
||||
/* clear the wakeup flags */
|
||||
if (lpuart_is_32(sport)) {
|
||||
val = lpuart32_read(&sport->port, UARTSTAT);
|
||||
lpuart32_write(&sport->port, val, UARTSTAT);
|
||||
stat = lpuart32_read(&sport->port, UARTSTAT);
|
||||
lpuart32_write(&sport->port, stat, UARTSTAT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user