github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-31 02:24:24 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: ti: k3-am62-ti-ipc-firmware: Refactor IPC cfg into new dtsi

Browse Source 
The TI K3 AM62 SoCs have multiple programmable remote processors like
R5F, M4F etc. The TI SDKs for AM62 SoCs offer sample firmwares which
could be run on these cores to demonstrate an "echo" IPC test. Those
firmware require certain memory carveouts to be reserved from system
memory, timers to be reserved, and certain mailbox configurations for
interrupt based messaging. These configurations could be different for a
different firmware.

While DT is not meant for system configurations, at least refactor these
configurations from board level DTS into a dtsi for now. This dtsi for
TI IPC firmware is board-independent and can be applied to all boards
from the same SoC Family. This gets rid of code duplication and allows
more freedom for users developing custom firmware (or no firmware) to
utilize system resources better; easily by swapping out this dtsi. To
maintain backward compatibility, the dtsi is included in all boards.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de> # phycore-am62x
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-32-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Beleswar Padhi 2025-09-08 19:58:23 +05:30 committed by Nishanth Menon
parent 6bd0449be3
commit 1d6161617c
5 changed files with 59 additions and 175 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
View File

@ -52,18 +52,6 @@ rtos_ipc_memory_region: memory@9c800000 {
no-map;
};
mcu_m4fss_dma_memory_region: memory@9cb00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cb00000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@9cc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cc00000 0x00 0xe00000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9da00000 0x00 0x100000>;
@ -245,20 +233,6 @@ cpsw3g_phy1: ethernet-phy@1 {
};
};
&mailbox0_cluster0 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&main_pktdma {
bootph-all;
};
@ -364,13 +338,6 @@ i2c_som_rtc: rtc@52 {
};
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@ -399,13 +366,4 @@ &sdhci0 {
status = "okay";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
status = "okay";
};
#include "k3-am62-ti-ipc-firmware.dtsi"

46
arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts
View File

@ -54,18 +54,6 @@ linux,cma {
linux,cma-default;
};
mcu_m4fss_dma_memory_region: memory@9cb00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cb00000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@9cc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cc00000 0x00 0xe00000>;
no-map;
};
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@ -298,20 +286,6 @@ &epwm2 {
pinctrl-0 = <&epwm2_pins_default>;
};
&mailbox0_cluster0 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
@ -362,24 +336,6 @@ &main_i2c2 {
status = "okay";
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
status = "okay";
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
@ -543,3 +499,5 @@ ldo4_reg: ldo4 {
};
};
};
#include "k3-am62-ti-ipc-firmware.dtsi"

52
arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs
*
* Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
&reserved_memory {
mcu_m4fss_dma_memory_region: memory@9cb00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cb00000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@9cc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cc00000 0x00 0xe00000>;
no-map;
};
};
&mailbox0_cluster0 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
status = "okay";
};

46
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
View File

@ -206,18 +206,6 @@ secure_ddr: optee@9e800000 {
no-map;
};
mcu_m4fss_dma_memory_region: memory@9cb00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cb00000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@9cc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cc00000 0x00 0xe00000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9da00000 0x00 0x100000>;
@ -1334,38 +1322,6 @@ &main_i2c3 {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
pinctrl-names = "default";
@ -1549,3 +1505,5 @@ &wkup_uart0 {
pinctrl-0 = <&pinctrl_wkup_uart0>;
status = "disabled";
};
#include "k3-am62-ti-ipc-firmware.dtsi"

46
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -58,18 +58,6 @@ linux,cma {
linux,cma-default;
};
mcu_m4fss_dma_memory_region: memory@9cb00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cb00000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@9cc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9cc00000 0x00 0xe00000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9da00000 0x00 0x100000>;
@ -477,38 +465,6 @@ cpsw3g_phy0: ethernet-phy@0 {
};
};
&mailbox0_cluster0 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_r5_0: mbox-r5-0 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&wkup_r5fss0 {
status = "okay";
};
&wkup_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
<&wkup_r5fss0_core0_memory_region>;
status = "okay";
};
&usbss0 {
bootph-all;
status = "okay";
@ -601,3 +557,5 @@ &epwm1 {
pinctrl-0 = <&main_epwm1_pins_default>;
status = "okay";
};
#include "k3-am62-ti-ipc-firmware.dtsi"