media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
fsl,mipi-phy-gpr from required properties and add new reg space, since
i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.

Keep the same restriction for other compatible strings.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250522-8qxp_camera-v5-8-d4be869fdb7e@nxp.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Robert Chiras 2025-05-22 13:56:46 -04:00 committed by Hans Verkuil
parent 859278460f
commit 1d2d96f599

View File

@ -16,11 +16,19 @@ description: |-
properties:
compatible:
enum:
- fsl,imx8mq-mipi-csi2
oneOf:
- enum:
- fsl,imx8mq-mipi-csi2
- fsl,imx8qxp-mipi-csi2
- items:
- const: fsl,imx8qm-mipi-csi2
- const: fsl,imx8qxp-mipi-csi2
reg:
maxItems: 1
items:
- description: MIPI CSI-2 RX host controller register.
- description: MIPI CSI-2 control and status register (csr).
minItems: 1
clocks:
items:
@ -46,6 +54,7 @@ properties:
- description: CORE_RESET reset register bit definition
- description: PHY_REF_RESET reset register bit definition
- description: ESC_RESET reset register bit definition
minItems: 1
fsl,mipi-phy-gpr:
description: |
@ -113,9 +122,30 @@ required:
- clock-names
- power-domains
- resets
- fsl,mipi-phy-gpr
- ports
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-mipi-csi2
then:
properties:
reg:
minItems: 2
resets:
maxItems: 1
else:
properties:
reg:
maxItems: 1
resets:
minItems: 3
required:
- fsl,mipi-phy-gpr
additionalProperties: false
examples: