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Microchip arm-soc updates for v6.18
This update includes: - low priority fixes to the PM code, in relation to recent addition of sam9x75 or sama7d65 SoCs - removal of the 2.5V regulator for low power modes since this is no longer supported -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCaMl72AAKCRAfOrpwrNPN DLzKAQCYcsnUOllsMHYnPkxO+js6t0nwzoOCUBvTZFKO+87r1gEA1aznYKK8FadV Mmp6RUB7c9VNgYh7nocK8lqNcUzdJQE= =Jmao -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjTC1kACgkQmmx57+YA GNn6Sg//b3fcj+8B2CdHK/hnBBaJUR7aJ/JCCxJjq8s/k14IMYoU+fEEwuyN3BII TwPGskMS10/APyqGL+m0rcIZoPGhnhO+Tm8ESjbAAygjrZlVW+T0PqwYeiCPEjjg SmSiS1gO4cLlL+7ZTbTf419gMC1/Nb5q+tAEdaHN5issOPmZEKa1ovkfmYt1FRNe q+musqyLLqYogmzKcmM+D03T6nht6HNhoszP2+cc1t6XpPvYL8alMH5sEiHsmIvR sWvw02OQPPMVortxJcYrab4EIXf3A+AW88oTPera9EbuO9yiHJ/ZEz0H37oNv3un 5/EVp1UUGnDV9LtYefGcYymazGxbwBcYdSk6blRoMlstFObNvOqIkQQzaNtfU/S6 +Tw4UT51zijxHHGCCJQJx5Pf8pZfntoE1kBg0HHwU+NNuaoGhwQPlYkltY1WFZzy LKTG7uZuCG9TjqpgPAPGgZo3uspQUPmWjTV0DN508Ek2jvjfUYpjePODSA00rDGB QqZGgkhvA/ykzWOju11UxWAWf2u3e1GNSTtu/rgGQ6dnU7uTpjmvxKZe8QFaCO8F OW4v5Wx1B0nINMm0xvUHwdzvoOJisVObmERYk7nomdsFUUqMheD5G2EE8whRmZVL NVpOChN5+zJrFOP7e4DIupCyOJcaHhkWYbrOfo4Nqg3WFyPuXqg= =3t5Z -----END PGP SIGNATURE----- Merge tag 'at91-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm Microchip arm-soc updates for v6.18 This update includes: - low priority fixes to the PM code, in relation to recent addition of sam9x75 or sama7d65 SoCs - removal of the 2.5V regulator for low power modes since this is no longer supported * tag 'at91-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: pm: Remove 2.5V regulator ARM: at91: pm: save and restore ACR during PLL disable/enable ARM: at91: pm: fix MCKx restore routine ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs Link: https://lore.kernel.org/r/20250916150328.27015-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
1cdfe53d57
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@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = {
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.version = AT91_PMC_V1,
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},
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{
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.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
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.uhp_udp_mask = AT91SAM926x_PMC_UHP,
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.mckr = 0x28,
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.version = AT91_PMC_V2,
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},
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@ -87,29 +87,6 @@ tmp3 .req r6
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.endm
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/**
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* Set state for 2.5V low power regulator
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* @ena: 0 - disable regulator
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* 1 - enable regulator
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*
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* Side effects: overwrites r7, r8, r9, r10
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*/
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.macro at91_2_5V_reg_set_low_power ena
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#ifdef CONFIG_SOC_SAMA7
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ldr r7, .sfrbu
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mov r8, #\ena
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ldr r9, [r7, #AT91_SFRBU_25LDOCR]
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orr r9, r9, #AT91_SFRBU_25LDOCR_LP
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cmp r8, #1
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beq lp_done_\ena
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bic r9, r9, #AT91_SFRBU_25LDOCR_LP
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lp_done_\ena:
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ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
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orr r9, r9, r10
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str r9, [r7, #AT91_SFRBU_25LDOCR]
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#endif
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.endm
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.macro at91_backup_set_lpm reg
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#ifdef CONFIG_SOC_SAMA7
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orr \reg, \reg, #0x200000
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@ -689,6 +666,10 @@ sr_dis_exit:
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bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
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str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
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/* save acr */
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ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
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str tmp2, .saved_acr
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/* save div. */
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mov tmp1, #0
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ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
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@ -758,7 +739,7 @@ sr_dis_exit:
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
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/* step 2. */
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ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
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ldr tmp1, .saved_acr
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str tmp1, [pmc, #AT91_PMC_PLL_ACR]
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/* step 3. */
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@ -904,7 +885,7 @@ e_done:
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/**
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* at91_mckx_ps_restore: restore MCKx settings
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*
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* Side effects: overwrites tmp1, tmp2
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* Side effects: overwrites tmp1, tmp2 and tmp3
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*/
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.macro at91_mckx_ps_restore
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#ifdef CONFIG_SOC_SAMA7
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@ -980,7 +961,7 @@ r_ps:
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bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
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orr tmp3, tmp3, tmp1
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orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
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str tmp2, [pmc, #AT91_PMC_MCR_V2]
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str tmp3, [pmc, #AT91_PMC_MCR_V2]
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wait_mckrdy tmp1
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@ -1019,9 +1000,6 @@ save_mck:
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at91_plla_disable
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/* Enable low power mode for 2.5V regulator. */
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at91_2_5V_reg_set_low_power 1
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ldr tmp3, .pm_mode
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cmp tmp3, #AT91_PM_ULP1
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beq ulp1_mode
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@ -1034,9 +1012,6 @@ ulp1_mode:
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b ulp_exit
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ulp_exit:
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/* Disable low power mode for 2.5V regulator. */
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at91_2_5V_reg_set_low_power 0
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ldr pmc, .pmc_base
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at91_plla_enable
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@ -1207,6 +1182,8 @@ ENDPROC(at91_pm_suspend_in_sram)
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#endif
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.saved_mckr:
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.word 0
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.saved_acr:
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.word 0
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.saved_pllar:
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.word 0
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.saved_sam9_lpr:
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@ -18,13 +18,6 @@
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#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */
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#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */
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#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */
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#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
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#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */
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#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */
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#define AT91_SFRBU_PD_VALUE_MSK (0x3)
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#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
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#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */
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#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */
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