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dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC

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This cache controller is also used on the StarFive JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Emil Renner Berthing 2022-12-20 09:12:44 +08:00 committed by Conor Dooley
parent 1b929c02af
commit 1caf002efa
1 changed files with 8 additions and 1 deletions
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9
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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@ -38,6 +38,10 @@ properties:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
- items:
- const: starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
@ -85,6 +89,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
then:
@ -105,7 +110,9 @@ allOf:
properties:
compatible:
contains:
const: sifive,fu740-c000-ccache
enum:
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
then:
properties: