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drm/amd/display: SubVP high refresh only if all displays >= 120hz
[Description] - SubVP high refresh should only be enabled if all displays are >= 120hz. We do not want to accidentally enables configs such as 60hz[SubVP] + 120hz[SubVP] - Ensure that the SubVP config generation code does not produce configs such as 60hz[SubVP] + 120hz[SubVP] - Also add admissibility checks to ensure these configs do not pass as valid configs Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
Alex Deucher
parent
e8c49e9eea
commit
1c982c9ffe
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@ -169,6 +169,10 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *conte
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bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);
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bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);
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bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);
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/* definitions for run time init of reg offsets */
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/* CLK SRC */
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@ -660,3 +660,104 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int widt
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return is_native_scaling;
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}
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/**
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* ************************************************************************************************
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* dcn32_subvp_drr_admissable: Determine if SubVP + DRR config is admissible
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*
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* @param [in]: dc: Current DC state
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* @param [in]: context: New DC state to be programmed
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*
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* SubVP + DRR is admissible under the following conditions:
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* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
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* - One display is SubVP
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* - Other display must have Freesync enabled
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*
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* @return: True if admissible, false otherwise
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*
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* ************************************************************************************************
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*/
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bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
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{
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bool result = false;
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uint32_t i;
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uint8_t subvp_count = 0;
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uint8_t non_subvp_pipes = 0;
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bool drr_pipe_found = false;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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if (!pipe->stream)
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continue;
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if (pipe->plane_state && !pipe->top_pipe) {
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if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
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subvp_count++;
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if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
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non_subvp_pipes++;
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if (pipe->stream->ignore_msa_timing_param &&
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(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
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drr_pipe_found = true;
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}
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}
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}
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}
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if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found)
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result = true;
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return result;
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}
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/**
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* ************************************************************************************************
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* dcn32_subvp_vblank_admissable: Determine if SubVP + Vblank config is admissible
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*
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* @param [in]: dc: Current DC state
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* @param [in]: context: New DC state to be programmed
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*
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* SubVP + Vblank is admissible under the following conditions:
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* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
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* - One display is SubVP
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* - Other display must not have Freesync capability
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* - DML must have output DRAM clock change support as SubVP + Vblank
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*
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* @return: True if admissible, false otherwise
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*
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* ************************************************************************************************
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*/
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bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)
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{
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bool result = false;
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uint32_t i;
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uint8_t subvp_count = 0;
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uint8_t non_subvp_pipes = 0;
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bool drr_pipe_found = false;
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struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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if (!pipe->stream)
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continue;
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if (pipe->plane_state && !pipe->top_pipe) {
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if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
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subvp_count++;
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if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
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non_subvp_pipes++;
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if (pipe->stream->ignore_msa_timing_param &&
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(pipe->stream->allow_freesync || pipe->stream->vrr_active_variable)) {
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drr_pipe_found = true;
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}
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}
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}
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}
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if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found &&
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vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
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result = true;
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return result;
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}
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@ -679,7 +679,6 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
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unsigned int max_frame_time = 0;
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bool valid_assignment_found = false;
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unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
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bool current_assignment_freesync = false;
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struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
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for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
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@ -720,19 +719,10 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
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struct dc_stream_state *stream = pipe->stream;
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unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
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(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
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if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
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if (frame_us > max_frame_time) {
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*index = i;
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max_frame_time = frame_us;
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valid_assignment_found = true;
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current_assignment_freesync = false;
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/* For the 2-Freesync display case, still choose the one with the
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* longest frame time
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*/
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} else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
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(current_assignment_freesync && frame_us > max_frame_time))) {
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*index = i;
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valid_assignment_found = true;
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current_assignment_freesync = true;
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}
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}
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}
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@ -878,11 +868,12 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
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*
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* Return: True if the SubVP + DRR config is schedulable, false otherwise
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*/
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static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
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static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
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{
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bool schedulable = false;
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uint32_t i;
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struct pipe_ctx *pipe = NULL;
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struct pipe_ctx *drr_pipe = NULL;
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struct dc_crtc_timing *main_timing = NULL;
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struct dc_crtc_timing *phantom_timing = NULL;
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struct dc_crtc_timing *drr_timing = NULL;
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@ -908,6 +899,19 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struc
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break;
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}
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// Find the DRR pipe
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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drr_pipe = &context->res_ctx.pipe_ctx[i];
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// We check for master pipe only
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if (!drr_pipe->stream || !drr_pipe->plane_state || drr_pipe->top_pipe || drr_pipe->prev_odm_pipe)
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continue;
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if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
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(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
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break;
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}
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main_timing = &pipe->stream->timing;
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phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
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drr_timing = &drr_pipe->stream->timing;
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@ -993,13 +997,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
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if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
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subvp_pipe = pipe;
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}
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// Use ignore_msa_timing_param and VRR active, or Freesync flag to identify as DRR On
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if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param &&
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(context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync ||
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context->res_ctx.pipe_ctx[vblank_index].stream->vrr_active_variable)) {
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// SUBVP + DRR case -- only allowed if run through DRR validation path
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schedulable = false;
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} else if (found) {
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if (found) {
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main_timing = &subvp_pipe->stream->timing;
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phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
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vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
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@ -1028,6 +1026,56 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
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return schedulable;
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}
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/**
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* ************************************************************************************************
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* subvp_subvp_admissable: Determine if subvp + subvp config is admissible
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*
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* @param [in]: dc: Current DC state
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* @param [in]: context: New DC state to be programmed
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*
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* SubVP + SubVP is admissible under the following conditions:
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* - All SubVP pipes are < 120Hz OR
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* - All SubVP pipes are >= 120hz
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*
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* @return: True if admissible, false otherwise
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*
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* ************************************************************************************************
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*/
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static bool subvp_subvp_admissable(struct dc *dc,
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struct dc_state *context)
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{
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bool result = false;
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uint32_t i;
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uint8_t subvp_count = 0;
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uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
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uint32_t refresh_rate = 0;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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if (!pipe->stream)
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continue;
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if (pipe->plane_state && !pipe->top_pipe &&
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pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
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refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
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pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
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/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
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if (refresh_rate < min_refresh)
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min_refresh = refresh_rate;
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if (refresh_rate > max_refresh)
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max_refresh = refresh_rate;
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subvp_count++;
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}
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}
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if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
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(min_refresh >= 120 && max_refresh >= 120)))
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result = true;
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return result;
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}
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/**
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* subvp_validate_static_schedulability - Check which SubVP case is calculated
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* and handle static analysis based on the case.
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@ -1046,11 +1094,12 @@ static bool subvp_validate_static_schedulability(struct dc *dc,
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struct dc_state *context,
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int vlevel)
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{
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bool schedulable = true; // true by default for single display case
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bool schedulable = false;
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struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
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uint32_t i, pipe_idx;
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uint8_t subvp_count = 0;
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uint8_t vactive_count = 0;
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uint8_t non_subvp_pipes = 0;
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for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
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@ -1058,14 +1107,18 @@ static bool subvp_validate_static_schedulability(struct dc *dc,
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if (!pipe->stream)
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continue;
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if (pipe->plane_state && !pipe->top_pipe &&
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pipe->stream->mall_stream_config.type == SUBVP_MAIN)
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subvp_count++;
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if (pipe->plane_state && !pipe->top_pipe) {
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if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
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subvp_count++;
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if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
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non_subvp_pipes++;
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}
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}
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// Count how many planes that aren't SubVP/phantom are capable of VACTIVE
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// switching (SubVP + VACTIVE unsupported). In situations where we force
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// SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
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if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
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if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
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pipe->stream->mall_stream_config.type == SUBVP_NONE) {
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vactive_count++;
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}
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@ -1074,13 +1127,14 @@ static bool subvp_validate_static_schedulability(struct dc *dc,
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if (subvp_count == 2) {
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// Static schedulability check for SubVP + SubVP case
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schedulable = subvp_subvp_schedulable(dc, context);
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} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
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// Static schedulability check for SubVP + VBLANK case. Also handle the case where
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// DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
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if (vactive_count > 0)
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schedulable = false;
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else
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schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
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} else if (subvp_count == 1 && non_subvp_pipes == 0) {
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// Single SubVP configs will be supported by default as long as it's suppported by DML
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schedulable = true;
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} else if (subvp_count == 1 && non_subvp_pipes == 1) {
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if (dcn32_subvp_drr_admissable(dc, context))
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schedulable = subvp_drr_schedulable(dc, context);
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else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
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schedulable = subvp_vblank_schedulable(dc, context);
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} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
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vactive_count > 0) {
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@ -1104,10 +1158,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
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unsigned int dc_pipe_idx = 0;
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int i = 0;
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bool found_supported_config = false;
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struct pipe_ctx *pipe = NULL;
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uint32_t non_subvp_pipes = 0;
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bool drr_pipe_found = false;
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uint32_t drr_pipe_index = 0;
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dc_assert_fp_enabled();
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@ -1197,31 +1247,12 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
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}
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}
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if (*vlevel < context->bw_ctx.dml.soc.num_states &&
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vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
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&& subvp_validate_static_schedulability(dc, context, *vlevel)) {
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if (*vlevel < context->bw_ctx.dml.soc.num_states
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&& subvp_validate_static_schedulability(dc, context, *vlevel))
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found_supported_config = true;
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} else if (*vlevel < context->bw_ctx.dml.soc.num_states) {
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/* Case where 1 SubVP is added, and DML reports MCLK unsupported or DRR is allowed.
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* This handles the case for SubVP + DRR, where the DRR display does not support MCLK
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* switch at it's native refresh rate / timing, or DRR is allowed for the non-subvp
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* display.
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*/
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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pipe = &context->res_ctx.pipe_ctx[i];
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if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
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pipe->stream->mall_stream_config.type == SUBVP_NONE) {
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non_subvp_pipes++;
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// Use ignore_msa_timing_param flag to identify as DRR
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if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) {
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drr_pipe_found = true;
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drr_pipe_index = i;
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}
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}
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}
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// If there is only 1 remaining non SubVP pipe that is DRR, check static
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// schedulability for SubVP + DRR.
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if (non_subvp_pipes == 1 && drr_pipe_found) {
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if (found_supported_config) {
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// For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
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if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
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/* find lowest vlevel that supports the config */
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for (i = *vlevel; i >= 0; i--) {
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if (vba->ModeSupport[i][vba->maxMpcComb]) {
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@ -1230,9 +1261,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
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break;
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}
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}
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found_supported_config = subvp_drr_schedulable(dc, context,
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&context->res_ctx.pipe_ctx[drr_pipe_index]);
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}
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}
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}
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@ -2882,16 +2910,34 @@ bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context
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{
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bool allow = false;
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uint32_t refresh_rate = 0;
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uint32_t min_refresh = subvp_high_refresh_list.min_refresh;
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uint32_t max_refresh = subvp_high_refresh_list.max_refresh;
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||||
uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
|
||||
uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
|
||||
uint32_t min_refresh = subvp_max_refresh;
|
||||
uint32_t i;
|
||||
|
||||
if (!dc->debug.disable_subvp_high_refresh && pipe->stream &&
|
||||
/* Only allow SubVP on high refresh displays if all connected displays
|
||||
* are considered "high refresh" (i.e. >= 120hz). We do not want to
|
||||
* allow combinations such as 120hz (SubVP) + 60hz (SubVP).
|
||||
*/
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (!pipe_ctx->stream)
|
||||
continue;
|
||||
refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
|
||||
pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
|
||||
/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
|
||||
|
||||
if (refresh_rate < min_refresh)
|
||||
min_refresh = refresh_rate;
|
||||
}
|
||||
|
||||
if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
|
||||
pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
|
||||
refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
|
||||
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
|
||||
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
|
||||
if (refresh_rate >= min_refresh && refresh_rate <= max_refresh) {
|
||||
if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
|
||||
for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
|
||||
uint32_t width = subvp_high_refresh_list.res[i].width;
|
||||
uint32_t height = subvp_high_refresh_list.res[i].height;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user