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drm/xe: Add frequency throttle reasons sysfs attributes
Add throttle reasons sysfs attributes under a separate directory. /device/tile<n>/gt<n>/freq0/throttle |- reason_pl1 |- reason_pl2 |- reason_pl4 |- reason_prochot |- reason_ratl |- reason_vr_tdc |- reason_vr_thermalert |- status v2: Remove unnecessary headers and clean-up action (Riana) Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Sujaritha Sundaresan
Rodrigo Vivi
parent
bef52b5c7a
commit
1c8e901903
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@ -78,6 +78,7 @@ xe-y += xe_bb.o \
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xe_gt_mcr.o \
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xe_gt_pagefault.o \
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xe_gt_sysfs.o \
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xe_gt_throttle_sysfs.o \
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xe_gt_tlb_invalidation.o \
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xe_gt_topology.o \
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xe_guc.o \
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@ -478,4 +478,16 @@
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#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
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#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
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#define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8)
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#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
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#define PROCHOT_MASK REG_BIT(0)
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#define THERMAL_LIMIT_MASK REG_BIT(1)
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#define RATL_MASK REG_BIT(5)
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#define VR_THERMALERT_MASK REG_BIT(6)
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#define VR_TDC_MASK REG_BIT(7)
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#define POWER_LIMIT_4_MASK REG_BIT(8)
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#define POWER_LIMIT_1_MASK REG_BIT(10)
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#define POWER_LIMIT_2_MASK REG_BIT(11)
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#define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030)
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#endif
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@ -13,6 +13,7 @@
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#include "xe_device_types.h"
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#include "xe_gt_sysfs.h"
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#include "xe_gt_throttle_sysfs.h"
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#include "xe_guc_pc.h"
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/**
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@ -213,4 +214,6 @@ void xe_gt_freq_init(struct xe_gt *gt)
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if (err)
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drm_warn(&xe->drm, "failed to add freq attrs to %s, err: %d\n",
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kobject_name(gt->freq), err);
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xe_gt_throttle_sysfs_init(gt);
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}
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251
drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c
Normal file
251
drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c
Normal file
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@ -0,0 +1,251 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include <drm/drm_managed.h>
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#include <regs/xe_gt_regs.h>
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gt_sysfs.h"
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#include "xe_gt_throttle_sysfs.h"
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#include "xe_mmio.h"
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/**
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* DOC: Xe GT Throttle
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*
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* Provides sysfs entries for frequency throttle reasons in GT
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*
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* device/gt#/freq0/throttle/status - Overall status
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* device/gt#/freq0/throttle/reason_pl1 - Frequency throttle due to PL1
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* device/gt#/freq0/throttle/reason_pl2 - Frequency throttle due to PL2
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* device/gt#/freq0/throttle/reason_pl4 - Frequency throttle due to PL4, Iccmax etc.
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* device/gt#/freq0/throttle/reason_thermal - Frequency throttle due to thermal
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* device/gt#/freq0/throttle/reason_prochot - Frequency throttle due to prochot
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* device/gt#/freq0/throttle/reason_ratl - Frequency throttle due to RATL
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* device/gt#/freq0/throttle/reason_vr_thermalert - Frequency throttle due to VR THERMALERT
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* device/gt#/freq0/throttle/reason_vr_tdc - Frequency throttle due to VR TDC
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*/
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static struct xe_gt *
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dev_to_gt(struct device *dev)
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{
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return kobj_to_gt(dev->kobj.parent);
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}
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static u32 read_perf_limit_reasons(struct xe_gt *gt)
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{
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u32 reg;
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if (xe_gt_is_media_type(gt))
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reg = xe_mmio_read32(gt, MTL_MEDIA_PERF_LIMIT_REASONS);
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else
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reg = xe_mmio_read32(gt, GT0_PERF_LIMIT_REASONS);
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return reg;
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}
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static u32 read_status(struct xe_gt *gt)
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{
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u32 status = read_perf_limit_reasons(gt) & GT0_PERF_LIMIT_REASONS_MASK;
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return status;
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}
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static u32 read_reason_pl1(struct xe_gt *gt)
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{
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u32 pl1 = read_perf_limit_reasons(gt) & POWER_LIMIT_1_MASK;
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return pl1;
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}
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static u32 read_reason_pl2(struct xe_gt *gt)
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{
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u32 pl2 = read_perf_limit_reasons(gt) & POWER_LIMIT_2_MASK;
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return pl2;
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}
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static u32 read_reason_pl4(struct xe_gt *gt)
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{
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u32 pl4 = read_perf_limit_reasons(gt) & POWER_LIMIT_4_MASK;
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return pl4;
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}
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static u32 read_reason_thermal(struct xe_gt *gt)
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{
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u32 thermal = read_perf_limit_reasons(gt) & THERMAL_LIMIT_MASK;
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return thermal;
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}
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static u32 read_reason_prochot(struct xe_gt *gt)
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{
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u32 prochot = read_perf_limit_reasons(gt) & PROCHOT_MASK;
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return prochot;
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}
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static u32 read_reason_ratl(struct xe_gt *gt)
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{
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u32 ratl = read_perf_limit_reasons(gt) & RATL_MASK;
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return ratl;
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}
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static u32 read_reason_vr_thermalert(struct xe_gt *gt)
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{
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u32 thermalert = read_perf_limit_reasons(gt) & VR_THERMALERT_MASK;
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return thermalert;
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}
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static u32 read_reason_vr_tdc(struct xe_gt *gt)
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{
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u32 tdc = read_perf_limit_reasons(gt) & VR_TDC_MASK;
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return tdc;
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}
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static ssize_t status_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool status = !!read_status(gt);
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return sysfs_emit(buff, "%u\n", status);
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}
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static DEVICE_ATTR_RO(status);
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static ssize_t reason_pl1_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool pl1 = !!read_reason_pl1(gt);
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return sysfs_emit(buff, "%u\n", pl1);
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}
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static DEVICE_ATTR_RO(reason_pl1);
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static ssize_t reason_pl2_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool pl2 = !!read_reason_pl2(gt);
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return sysfs_emit(buff, "%u\n", pl2);
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}
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static DEVICE_ATTR_RO(reason_pl2);
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static ssize_t reason_pl4_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool pl4 = !!read_reason_pl4(gt);
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return sysfs_emit(buff, "%u\n", pl4);
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}
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static DEVICE_ATTR_RO(reason_pl4);
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static ssize_t reason_thermal_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool thermal = !!read_reason_thermal(gt);
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return sysfs_emit(buff, "%u\n", thermal);
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}
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static DEVICE_ATTR_RO(reason_thermal);
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static ssize_t reason_prochot_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool prochot = !!read_reason_prochot(gt);
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return sysfs_emit(buff, "%u\n", prochot);
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}
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static DEVICE_ATTR_RO(reason_prochot);
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static ssize_t reason_ratl_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool ratl = !!read_reason_ratl(gt);
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return sysfs_emit(buff, "%u\n", ratl);
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}
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static DEVICE_ATTR_RO(reason_ratl);
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static ssize_t reason_vr_thermalert_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool thermalert = !!read_reason_vr_thermalert(gt);
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return sysfs_emit(buff, "%u\n", thermalert);
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}
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static DEVICE_ATTR_RO(reason_vr_thermalert);
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static ssize_t reason_vr_tdc_show(struct device *dev,
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struct device_attribute *attr,
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char *buff)
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{
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struct xe_gt *gt = dev_to_gt(dev);
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bool tdc = !!read_reason_vr_tdc(gt);
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return sysfs_emit(buff, "%u\n", tdc);
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}
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static DEVICE_ATTR_RO(reason_vr_tdc);
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static struct attribute *throttle_attrs[] = {
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&dev_attr_status.attr,
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&dev_attr_reason_pl1.attr,
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&dev_attr_reason_pl2.attr,
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&dev_attr_reason_pl4.attr,
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&dev_attr_reason_thermal.attr,
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&dev_attr_reason_prochot.attr,
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&dev_attr_reason_ratl.attr,
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&dev_attr_reason_vr_thermalert.attr,
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&dev_attr_reason_vr_tdc.attr,
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NULL
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};
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static const struct attribute_group throttle_group_attrs = {
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.name = "throttle",
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.attrs = throttle_attrs,
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};
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static void gt_throttle_sysfs_fini(struct drm_device *drm, void *arg)
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{
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struct xe_gt *gt = arg;
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sysfs_remove_group(gt->freq, &throttle_group_attrs);
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}
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void xe_gt_throttle_sysfs_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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int err;
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err = sysfs_create_group(gt->freq, &throttle_group_attrs);
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if (err) {
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drm_warn(&xe->drm, "failed to register throttle sysfs, err: %d\n", err);
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return;
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}
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err = drmm_add_action_or_reset(&xe->drm, gt_throttle_sysfs_fini, gt);
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if (err)
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drm_warn(&xe->drm, "%s: drmm_add_action_or_reset failed, err: %d\n",
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__func__, err);
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}
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16
drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h
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16
drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GT_THROTTLE_SYSFS_H_
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#define _XE_GT_THROTTLE_SYSFS_H_
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#include <drm/drm_managed.h>
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struct xe_gt;
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void xe_gt_throttle_sysfs_init(struct xe_gt *gt);
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#endif /* _XE_GT_THROTTLE_SYSFS_H_ */
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