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drm/amd/display: adjust floating point format for gamut remap when needed

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[Why]
The MPCCs different gamut remap matrices allow for S2D13 and S3D12 floating
point formats, but only S2D13 is used. There may be cases where more
integer bits are required.

[How]
Switch to S3D12 if any entries in the remap matrix cannot fit in S2D13.
Otherwise, prefer the extra precision of S2D13. Communicate the max value
that hw can support to dm via dc color caps.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Clay King 2026-07-15 17:41:55 -04:00 committed by Alex Deucher
parent df1bdfaf57
commit 1c5e6cd829
27 changed files with 186 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
drivers/gpu/drm/amd/display/dc/basics/conversion.c
View File

@ -26,11 +26,7 @@
#include "dm_services.h"
#include "basics/conversion.h"
#define DIVIDER 10000
/* S2D13 value in [-3.00...0.9999] */
#define S2D13_MIN (-3 * DIVIDER)
#define S2D13_MAX (3 * DIVIDER)
uint16_t fixed_point_to_int_frac(
struct fixed31_32 arg,
@ -74,28 +70,44 @@ uint16_t fixed_point_to_int_frac(
return result;
}
/*
* convert_float_matrix - This converts a double into HW register spec defined format S2D13.
* convert_float_matrix - This converts a double into HW register spec defined format S2D13 / S3D12.
*/
void convert_float_matrix(
uint16_t *matrix,
struct fixed31_32 *flt,
const struct fixed31_32 *flt,
enum cm_gamut_coef_format format,
uint32_t buffer_size)
{
const struct fixed31_32 min_2_13 =
dc_fixpt_from_fraction(S2D13_MIN, DIVIDER);
const struct fixed31_32 max_2_13 =
dc_fixpt_from_fraction(S2D13_MAX, DIVIDER);
struct fixed31_32 min;
struct fixed31_32 max;
uint8_t num_int_bits;
uint8_t num_dec_bits;
uint32_t i;
if (format == CM_GAMUT_REMAP_COEF_FORMAT_S2_13) {
min = dc_fixpt_from_fraction(S2D13_MIN, DIVIDER);
max = dc_fixpt_from_fraction(S2D13_MAX, DIVIDER);
num_int_bits = 2;
num_dec_bits = 13;
} else if (format == CM_GAMUT_REMAP_COEF_FORMAT_S3_12) {
min = dc_fixpt_from_fraction(S3D12_MIN, DIVIDER);
max = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
num_int_bits = 3;
num_dec_bits = 12;
} else {
ASSERT(false);
return;
}
for (i = 0; i < buffer_size; ++i) {
uint32_t reg_value =
fixed_point_to_int_frac(
dc_fixpt_clamp(
flt[i],
min_2_13,
max_2_13),
2,
13);
min,
max),
num_int_bits,
num_dec_bits);
matrix[i] = (uint16_t)reg_value;
}
@ -129,10 +141,27 @@ static struct fixed31_32 int_frac_to_fixed_point(uint16_t arg,
*/
void convert_hw_matrix(struct fixed31_32 *matrix,
uint16_t *reg,
enum cm_gamut_coef_format format,
uint32_t buffer_size)
{
for (uint32_t i = 0; i < buffer_size; ++i)
matrix[i] = int_frac_to_fixed_point(reg[i], 2, 13);
uint8_t num_int_bits;
uint8_t num_dec_bits;
uint32_t i;
if (format == CM_GAMUT_REMAP_COEF_FORMAT_S2_13) {
num_int_bits = 2;
num_dec_bits = 13;
} else if (format == CM_GAMUT_REMAP_COEF_FORMAT_S3_12) {
num_int_bits = 3;
num_dec_bits = 12;
} else {
ASSERT(false);
return;
}
for (i = 0; i < buffer_size; ++i)
matrix[i] = int_frac_to_fixed_point(reg[i],
num_int_bits, num_dec_bits);
}
static uint32_t find_gcd(uint32_t a, uint32_t b)

12
drivers/gpu/drm/amd/display/dc/basics/conversion.h
View File

@ -28,6 +28,14 @@
#include "include/fixed31_32.h"
#define DIVIDER 10000
#define S2D13_MIN (-4 * DIVIDER)
#define S2D13_MAX (39999)
#define S3D12_MIN (-8 * DIVIDER)
#define S3D12_MAX (79998)
uint16_t fixed_point_to_int_frac(
struct fixed31_32 arg,
uint8_t integer_bits,
@ -35,7 +43,8 @@ uint16_t fixed_point_to_int_frac(
void convert_float_matrix(
uint16_t *matrix,
struct fixed31_32 *flt,
const struct fixed31_32 *flt,
enum cm_gamut_coef_format format,
uint32_t buffer_size);
void reduce_fraction(uint32_t num, uint32_t den,
@ -43,6 +52,7 @@ void reduce_fraction(uint32_t num, uint32_t den,
void convert_hw_matrix(struct fixed31_32 *matrix,
uint16_t *reg,
enum cm_gamut_coef_format format,
uint32_t buffer_size);
static inline unsigned int log_2(unsigned int num)

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -315,6 +315,7 @@ struct mpc_color_caps {
struct lut3d_caps mcm_3d_lut_caps;
struct lut3d_caps rmcm_3d_lut_caps;
bool preblend;
struct fixed31_32 max_gamut_remap_coeff;
};
/**

4
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
View File

@ -1145,8 +1145,8 @@ static void dce_transform_set_gamut_remap(
for (i = 0; i < GAMUT_MATRIX_SIZE; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
convert_float_matrix(
arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
convert_float_matrix(arr_reg_val, arr_matrix,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, GAMUT_MATRIX_SIZE);
program_gamut_remap(xfm_dce, arr_reg_val);
}

8
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
View File

@ -171,8 +171,8 @@ void dpp1_cm_set_gamut_remap(
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
convert_float_matrix(
arr_reg_val, arr_matrix, 12);
convert_float_matrix(arr_reg_val, arr_matrix,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, 12);
program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
}
@ -242,8 +242,8 @@ void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,
}
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
convert_hw_matrix(adjust->temperature_matrix,
arr_reg_val, ARRAY_SIZE(arr_reg_val));
convert_hw_matrix(adjust->temperature_matrix, arr_reg_val,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, ARRAY_SIZE(arr_reg_val));
}
static void dpp1_cm_program_color_matrix(

8
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
View File

@ -227,8 +227,8 @@ void dpp2_cm_set_gamut_remap(
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
convert_float_matrix(
arr_reg_val, arr_matrix, 12);
convert_float_matrix(arr_reg_val, arr_matrix,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, 12);
program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A);
}
@ -285,8 +285,8 @@ void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,
}
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
convert_hw_matrix(adjust->temperature_matrix,
arr_reg_val, ARRAY_SIZE(arr_reg_val));
convert_hw_matrix(adjust->temperature_matrix, arr_reg_val,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, ARRAY_SIZE(arr_reg_val));
}
void dpp2_program_input_csc(

8
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
View File

@ -392,8 +392,8 @@ void dpp3_cm_set_gamut_remap(
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
convert_float_matrix(
arr_reg_val, arr_matrix, 12);
convert_float_matrix(arr_reg_val, arr_matrix,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, 12);
//current coefficient set in use
REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
@ -460,6 +460,6 @@ void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
}
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
convert_hw_matrix(adjust->temperature_matrix,
arr_reg_val, ARRAY_SIZE(arr_reg_val));
convert_hw_matrix(adjust->temperature_matrix, arr_reg_val,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, ARRAY_SIZE(arr_reg_val));
}

3
drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
View File

@ -371,7 +371,8 @@ void dwb3_set_gamut_remap(
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust.temperature_matrix[i];
convert_float_matrix(arr_reg_val, arr_matrix, 12);
convert_float_matrix(arr_reg_val, arr_matrix,
CM_GAMUT_REMAP_COEF_FORMAT_S2_13, 12);
REG_GET(DWB_GAMUT_REMAP_MODE, DWB_GAMUT_REMAP_MODE_CURRENT, &current_mode);

44
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
View File

@ -1067,7 +1067,8 @@ static void program_gamut_remap(
struct dcn30_mpc *mpc30,
int mpcc_id,
const uint16_t *regval,
uint32_t select)
uint32_t select,
enum cm_gamut_coef_format coef_format)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
@ -1117,9 +1118,11 @@ static void program_gamut_remap(
&gam_regs);
}
//select coefficient set to use
// select coefficient set + format to use
REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,
MPCC_GAMUT_REMAP_MODE, selection);
REG_SET(MPCC_GAMUT_REMAP_COEF_FORMAT[mpcc_id], 0,
MPCC_GAMUT_REMAP_COEF_FORMAT, coef_format);
}
void mpc3_set_gamut_remap(
@ -1130,18 +1133,26 @@ void mpc3_set_gamut_remap(
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
int i = 0;
uint32_t gamut_mode;
uint16_t hw_matrix[12];
enum cm_gamut_coef_format coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
struct fixed31_32 abs_max_coef = {0};
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS);
program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS, coef_format);
else {
struct fixed31_32 arr_matrix[12];
uint16_t arr_reg_val[12];
// take largest absolute value of coefficient in temperature matrix
// if S2D13 cannot fit value, use S3D12
for (i = 0; i < 12; i++) {
if (dc_fixpt_le(abs_max_coef, dc_fixpt_abs(adjust->temperature_matrix[i])))
abs_max_coef = dc_fixpt_abs(adjust->temperature_matrix[i]);
}
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
if (dc_fixpt_le(abs_max_coef, dc_fixpt_from_fraction(S2D13_MAX, DIVIDER)))
coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
else
coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S3_12;
convert_float_matrix(
arr_reg_val, arr_matrix, 12);
convert_float_matrix(hw_matrix, adjust->temperature_matrix, coef_format, 12);
//current coefficient set in use
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, &gamut_mode);
@ -1153,19 +1164,21 @@ void mpc3_set_gamut_remap(
else
gamut_mode = 1;
program_gamut_remap(mpc30, mpcc_id, arr_reg_val, gamut_mode);
program_gamut_remap(mpc30, mpcc_id, hw_matrix, gamut_mode, coef_format);
}
}
static void read_gamut_remap(struct dcn30_mpc *mpc30,
int mpcc_id,
uint16_t *regval,
uint32_t *select)
uint32_t *select,
enum cm_gamut_coef_format *coef_format)
{
struct color_matrices_reg gam_regs;
//current coefficient set in use
//current coefficient set in use + format
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, select);
REG_GET(MPCC_GAMUT_REMAP_COEF_FORMAT[mpcc_id], MPCC_GAMUT_REMAP_COEF_FORMAT, coef_format);
gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A;
gam_regs.masks.csc_c11 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C11_A;
@ -1202,8 +1215,9 @@ void mpc3_get_gamut_remap(struct mpc *mpc,
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
uint16_t arr_reg_val[12] = {0};
uint32_t select;
enum cm_gamut_coef_format coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select);
read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select, &coef_format);
if (select == GAMUT_REMAP_BYPASS) {
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
@ -1211,8 +1225,8 @@ void mpc3_get_gamut_remap(struct mpc *mpc,
}
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
convert_hw_matrix(adjust->temperature_matrix,
arr_reg_val, ARRAY_SIZE(arr_reg_val));
convert_hw_matrix(adjust->temperature_matrix, arr_reg_val,
coef_format, ARRAY_SIZE(arr_reg_val));
}
bool mpc3_program_3dlut(

69
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
View File

@ -302,7 +302,8 @@ void mpc_program_gamut_remap(
unsigned int mpcc_id,
const uint16_t *regval,
enum mpcc_gamut_remap_id gamut_remap_block_id,
enum mpcc_gamut_remap_mode_select mode_select)
enum mpcc_gamut_remap_mode_select mode_select,
enum cm_gamut_coef_format coef_format)
{
struct color_matrices_reg gamut_regs;
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
@ -339,8 +340,11 @@ void mpc_program_gamut_remap(
regval,
&gamut_regs);
//select coefficient set to use, set A (MODE_1) or set B (MODE_2)
REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, MPCC_GAMUT_REMAP_MODE, mode_select);
//select coefficient set to use, set A (MODE_1) or set B (MODE_2) + format
REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,
MPCC_GAMUT_REMAP_MODE, mode_select);
REG_SET(MPCC_GAMUT_REMAP_COEF_FORMAT[mpcc_id], 0,
MPCC_GAMUT_REMAP_COEF_FORMAT, coef_format);
break;
case MPCC_MCM_FIRST_GAMUT_REMAP:
@ -373,9 +377,11 @@ void mpc_program_gamut_remap(
regval,
&gamut_regs);
//select coefficient set to use, set A (MODE_1) or set B (MODE_2)
//select coefficient set to use, set A (MODE_1) or set B (MODE_2) + format
REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id], 0,
MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mode_select);
REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[mpcc_id], 0,
MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, coef_format);
break;
case MPCC_MCM_SECOND_GAMUT_REMAP:
@ -408,9 +414,11 @@ void mpc_program_gamut_remap(
regval,
&gamut_regs);
//select coefficient set to use, set A (MODE_1) or set B (MODE_2)
//select coefficient set to use, set A (MODE_1) or set B (MODE_2) + format
REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id], 0,
MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mode_select);
REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[mpcc_id], 0,
MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, coef_format);
break;
default:
@ -426,19 +434,28 @@ void mpc401_set_gamut_remap(
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
unsigned int i = 0;
uint32_t mode_select = 0;
uint16_t hw_matrix[12];
enum cm_gamut_coef_format coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
struct fixed31_32 abs_max_coef = {0};
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) {
/* Bypass / Disable if type is bypass or hw */
mpc_program_gamut_remap(mpc, mpcc_id, NULL,
adjust->mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0);
mpc_program_gamut_remap(mpc, mpcc_id, NULL, adjust->mpcc_gamut_remap_block_id,
MPCC_GAMUT_REMAP_MODE_SELECT_0, coef_format);
} else {
struct fixed31_32 arr_matrix[12];
uint16_t arr_reg_val[12];
// take largest absolute value of coefficient in temperature matrix
// if S2D13 cannot fit value, use S3D12
for (i = 0; i < 12; i++) {
if (dc_fixpt_le(abs_max_coef, dc_fixpt_abs(adjust->temperature_matrix[i])))
abs_max_coef = dc_fixpt_abs(adjust->temperature_matrix[i]);
}
for (i = 0; i < 12; i++)
arr_matrix[i] = adjust->temperature_matrix[i];
if (dc_fixpt_le(abs_max_coef, dc_fixpt_from_fraction(S2D13_MAX, DIVIDER)))
coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
else
coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S3_12;
convert_float_matrix(arr_reg_val, arr_matrix, 12);
convert_float_matrix(hw_matrix, adjust->temperature_matrix, coef_format, 12);
switch (adjust->mpcc_gamut_remap_block_id) {
case MPCC_OGAM_GAMUT_REMAP:
@ -463,8 +480,8 @@ void mpc401_set_gamut_remap(
else
mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2;
mpc_program_gamut_remap(mpc, mpcc_id, arr_reg_val,
adjust->mpcc_gamut_remap_block_id, mode_select);
mpc_program_gamut_remap(mpc, mpcc_id, hw_matrix,
adjust->mpcc_gamut_remap_block_id, mode_select, coef_format);
}
}
@ -472,7 +489,8 @@ void mpc_read_gamut_remap(struct mpc *mpc,
int mpcc_id,
uint16_t *regval,
enum mpcc_gamut_remap_id gamut_remap_block_id,
uint32_t *mode_select)
uint32_t *mode_select,
enum cm_gamut_coef_format *coef_format)
{
struct color_matrices_reg gamut_regs = {0};
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
@ -480,7 +498,10 @@ void mpc_read_gamut_remap(struct mpc *mpc,
switch (gamut_remap_block_id) {
case MPCC_OGAM_GAMUT_REMAP:
//current coefficient set in use
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, mode_select);
REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id],
MPCC_GAMUT_REMAP_MODE_CURRENT, mode_select);
REG_GET(MPCC_GAMUT_REMAP_COEF_FORMAT[mpcc_id],
MPCC_GAMUT_REMAP_COEF_FORMAT, coef_format);
gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A;
gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_GAMUT_REMAP_C11_A;
@ -503,7 +524,9 @@ void mpc_read_gamut_remap(struct mpc *mpc,
case MPCC_MCM_FIRST_GAMUT_REMAP:
REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id],
MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mode_select);
MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mode_select);
REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[mpcc_id],
MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, coef_format);
gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;
gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;
@ -526,7 +549,9 @@ void mpc_read_gamut_remap(struct mpc *mpc,
case MPCC_MCM_SECOND_GAMUT_REMAP:
REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id],
MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mode_select);
MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mode_select);
REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[mpcc_id],
MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, coef_format);
gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;
gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;
@ -565,8 +590,10 @@ void mpc401_get_gamut_remap(struct mpc *mpc,
{
uint16_t arr_reg_val[12] = {0};
uint32_t mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_0;
enum cm_gamut_coef_format coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;
mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select);
mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val,
adjust->mpcc_gamut_remap_block_id, &mode_select, &coef_format);
if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
@ -574,8 +601,8 @@ void mpc401_get_gamut_remap(struct mpc *mpc,
}
adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
convert_hw_matrix(adjust->temperature_matrix,
arr_reg_val, ARRAY_SIZE(arr_reg_val));
convert_hw_matrix(adjust->temperature_matrix, arr_reg_val,
coef_format, ARRAY_SIZE(arr_reg_val));
}
static const struct mpc_funcs dcn401_mpc_funcs = {

6
drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
View File

@ -242,13 +242,15 @@ void mpc_program_gamut_remap(
unsigned int mpcc_id,
const uint16_t *regval,
enum mpcc_gamut_remap_id gamut_remap_block_id,
enum mpcc_gamut_remap_mode_select mode_select);
enum mpcc_gamut_remap_mode_select mode_select,
enum cm_gamut_coef_format coef_format);
void mpc_read_gamut_remap(struct mpc *mpc,
int mpcc_id,
uint16_t *regval,
enum mpcc_gamut_remap_id gamut_remap_block_id,
uint32_t *mode_select);
uint32_t *mode_select,
enum cm_gamut_coef_format *coef_format);
void mpc401_get_3dlut_fast_load_status(
struct mpc *mpc,

2
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn20/dcn20_resource.h"
#include "dcn30_resource.h"
@ -2515,6 +2516,7 @@ static bool dcn30_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.dp_hdmi21_pcon_support = true;
dc->caps.max_v_total = (1 << 15) - 1;

2
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_resource.h"
#include "dcn301_resource.h"
@ -1516,6 +1517,7 @@ static bool dcn301_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.dp_hdmi21_pcon_support = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
View File

@ -27,6 +27,7 @@
#include "dcn302_resource.h"
#include "dcn302/dcn302_dccg.h"
#include "irq/dcn302/irq_service_dcn302.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_dio_link_encoder.h"
#include "dcn30/dcn30_dio_stream_encoder.h"
@ -1416,6 +1417,7 @@ static bool dcn302_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.dp_hdmi21_pcon_support = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
View File

@ -27,6 +27,7 @@
#include "dcn303_resource.h"
#include "dcn303/dcn303_dccg.h"
#include "irq/dcn303/irq_service_dcn303.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_dio_link_encoder.h"
#include "dcn30/dcn30_dio_stream_encoder.h"
@ -1360,6 +1361,7 @@ static bool dcn303_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.dp_hdmi21_pcon_support = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn31_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2123,6 +2124,7 @@ static bool dcn31_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 2;
dc->caps.num_of_dpias_per_host_router = 2;

2
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
View File

@ -33,6 +33,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn314_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2051,6 +2052,7 @@ static bool dcn314_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.max_disp_clock_khz_at_vmin = 650000;

2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn315_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2095,6 +2096,7 @@ static bool dcn315_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->config.no_native422_support = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn316_resource.h"
#include "dcn20/dcn20_resource.h"
@ -1969,6 +1970,7 @@ static bool dcn316_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
/* read VBIOS LTTPR caps */
{

2
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
View File

@ -32,6 +32,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn32_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2448,6 +2449,7 @@ static bool dcn32_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
View File

@ -31,6 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn32/dcn32_resource.h"
#include "dcn321_resource.h"
@ -1939,6 +1940,7 @@ static bool dcn321_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
/* HACK: Force FRL support until BIOS is ready. */
dc->config.force_hdmi21_frl_enc_enable = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@ -32,6 +32,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn35_resource.h"
#include "dml2_0/dml2_wrapper.h"
@ -2078,6 +2079,7 @@ static bool dcn35_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 2;
dc->caps.num_of_dpias_per_host_router = 2;

2
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@ -10,6 +10,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn351_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2051,6 +2052,7 @@ static bool dcn351_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 2;
dc->caps.num_of_dpias_per_host_router = 2;

2
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
View File

@ -10,6 +10,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn36_resource.h"
#include "dml2_0/dml2_wrapper.h"
@ -2048,6 +2049,7 @@ static bool dcn36_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 2;
dc->caps.num_of_dpias_per_host_router = 2;

2
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -10,6 +10,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn401_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2131,6 +2132,7 @@ static bool dcn401_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.color.mpc.preblend = true;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
/* HACK: Force FRL support until BIOS is ready. */
dc->config.force_hdmi21_frl_enc_enable = true;
dc->config.use_spl = true;

2
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
View File

@ -9,6 +9,7 @@
#include "dcn42/dcn42_init.h"
#include "resource.h"
#include "basics/conversion.h"
#include "include/irq_service_interface.h"
#include "dcn42_resource.h"
@ -2110,6 +2111,7 @@ static bool dcn42_resource_construct(
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 3;
dc->caps.num_of_dpias_per_host_router = 2;

2
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
View File

@ -13,6 +13,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "basics/conversion.h"
#include "dcn42b_resource.h"
#include "dcn20/dcn20_resource.h"
@ -2080,6 +2081,7 @@ static bool dcn42b_resource_construct(
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1;
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1;
dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1;
dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
dc->caps.num_of_host_routers = 0;
dc->caps.num_of_dpias_per_host_router = 0;