From 1c40a2d06d0313cdb19aec4f0bb81959a0da1765 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 7 Aug 2026 19:24:31 -0600 Subject: [PATCH] dt-bindings: riscv: add Smcntrpmf ISA extension description Add the description for Smcntrpmf ISA extension Acked-by: Rob Herring (Arm) Signed-off-by: Atish Patra Link: https://patch.msgid.link/20260807-counter_delegation-v9-7-58658104e487@meta.com Signed-off-by: Paul Walmsley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ccff2be1224d..eee65cf73d6c 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smcntrpmf + description: | + The standard Smcntrpmf machine-level extension for the machine mode + to enable privilege mode filtering for cycle and instret counters as + ratified in the 20240326 version of the privileged ISA specification. + - const: smcsrind description: | The standard Smcsrind machine-level extension extends the