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dt-bindings: Convert gpio-mmio to yaml
This is a generic binding for simple MMIO GPIO controllers. Although we have a single driver for these controllers, they were previously spread over several files. Consolidate them. The register descriptions are adapted from the comments in the source. There is no set order for the registers, and some registers may be omitted. Because of this, reg-names is mandatory, and no order is specified. Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345 has moved. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Sean Anderson
Bartosz Golaszewski
parent
f8d1af2475
commit
1c23553a66
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@ -1,10 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
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$id: http://devicetree.org/schemas/gpio/brcm,bcm63xx-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom BCM6345 GPIO controller
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title: Broadcom BCM63xx GPIO controller
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maintainers:
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- Álvaro Fernández Rojas <noltari@gmail.com>
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@ -18,8 +18,6 @@ description: |+
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BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
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and/or written, and the direction changed from input to output.
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BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
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and/or written, and the direction changed from input to output.
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BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
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and dirout registers, where GPIO state can be read and/or written, and the
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direction changed from input to output.
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@ -29,7 +27,6 @@ properties:
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enum:
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- brcm,bcm6318-gpio
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- brcm,bcm6328-gpio
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- brcm,bcm6345-gpio
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- brcm,bcm6358-gpio
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- brcm,bcm6362-gpio
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- brcm,bcm6368-gpio
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@ -63,17 +60,6 @@ required:
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additionalProperties: false
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examples:
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- |
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gpio@fffe0406 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0xfffe0406 2>, <0xfffe040a 2>;
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native-endian;
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gpio-controller;
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#gpio-cells = <2>;
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};
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- |
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gpio@0 {
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compatible = "brcm,bcm63268-gpio";
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117
Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
Normal file
117
Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
Normal file
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@ -0,0 +1,117 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic MMIO GPIO
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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- Bartosz Golaszewski <brgl@bgdev.pl>
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description:
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Some simple GPIO controllers may consist of a single data register or a pair
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of set/clear-bit registers. Such controllers are common for glue logic in
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FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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NAND-style parallel busses.
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properties:
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compatible:
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enum:
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- brcm,bcm6345-gpio
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- ni,169445-nand-gpio
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- wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
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big-endian: true
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'#gpio-cells':
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const: 2
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gpio-controller: true
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little-endian: true
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reg:
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minItems: 1
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description:
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A list of registers in the controller. The width of each register is
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determined by its size. All registers must have the same width. The number
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of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
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items:
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- description:
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Register to READ the value of the GPIO lines. If GPIO line is high,
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the bit will be set. If the GPIO line is low, the bit will be cleared.
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This register may also be used to drive GPIOs if the SET register is
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omitted.
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- description:
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Register to SET the value of the GPIO lines. Setting a bit in this
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register will drive the GPIO line high.
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- description:
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Register to CLEAR the value of the GPIO lines. Setting a bit in this
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register will drive the GPIO line low. If this register is omitted,
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the SET register will be used to clear the GPIO lines as well, by
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actively writing the line with 0.
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- description:
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Register to set the line as OUTPUT. Setting a bit in this register
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will turn that line into an output line. Conversely, clearing a bit
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will turn that line into an input.
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- description:
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Register to set this line as INPUT. Setting a bit in this register
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will turn that line into an input line. Conversely, clearing a bit
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will turn that line into an output.
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reg-names:
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minItems: 1
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maxItems: 5
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items:
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enum:
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- dat
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- set
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- clr
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- dirout
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- dirin
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native-endian: true
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no-output:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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If this property is present, the controller cannot drive the GPIO lines.
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required:
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- compatible
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- reg
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- reg-names
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- '#gpio-cells'
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- gpio-controller
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additionalProperties: false
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examples:
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- |
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gpio@1f300010 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300010 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio@e0100000 {
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compatible = "wd,mbl-gpio";
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reg-names = "dat";
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reg = <0xe0100000 0x1>;
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#gpio-cells = <2>;
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gpio-controller;
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no-output;
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};
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gpio@fffe0406 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0xfffe0406 2>, <0xfffe040a 2>;
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native-endian;
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gpio-controller;
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#gpio-cells = <2>;
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};
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@ -1,38 +0,0 @@
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Bindings for the National Instruments 169445 GPIO NAND controller
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The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
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for input (the ready signal) and one for output (control signals). It is
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intended to be used with the GPIO NAND driver.
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Required properties:
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- compatible: should be "ni,169445-nand-gpio"
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- reg-names: must contain
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"dat" - data register
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- reg: address + size pairs describing the GPIO register sets;
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order must correspond with the order of entries in reg-names
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- #gpio-cells: must be set to 2. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a gpio controller.
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Optional properties:
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- no-output: disables driving output on the pins
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Examples:
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gpio1: nand-gpio-out@1f300010 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300010 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: nand-gpio-in@1f300014 {
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compatible = "ni,169445-nand-gpio";
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reg = <0x1f300014 0x4>;
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reg-names = "dat";
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gpio-controller;
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#gpio-cells = <2>;
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no-output;
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};
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@ -1,38 +0,0 @@
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Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
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The Western Digital MyBook Live has two memory-mapped GPIO controllers.
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Both GPIO controller only have a single 8-bit data register, where GPIO
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state can be read and/or written.
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Required properties:
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- compatible: should be "wd,mbl-gpio"
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- reg-names: must contain
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"dat" - data register
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- reg: address + size pairs describing the GPIO register sets;
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order must correspond with the order of entries in reg-names
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- #gpio-cells: must be set to 2. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a gpio controller.
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Optional properties:
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- no-output: GPIOs are read-only.
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Examples:
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gpio0: gpio0@e0000000 {
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compatible = "wd,mbl-gpio";
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reg-names = "dat";
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reg = <0xe0000000 0x1>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio1: gpio1@e0100000 {
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compatible = "wd,mbl-gpio";
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reg-names = "dat";
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reg = <0xe0100000 0x1>;
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#gpio-cells = <2>;
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gpio-controller;
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no-output;
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};
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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@ -35,11 +35,11 @@ patternProperties:
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"^gpio@[0-9a-f]+$":
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# Child node
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type: object
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$ref: "../gpio/brcm,bcm6345-gpio.yaml"
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$ref: "../gpio/brcm,bcm63xx-gpio.yaml"
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description:
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GPIO controller for the SoC GPIOs. This child node definition
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should follow the bindings specified in
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Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml.
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"^pinctrl@[0-9a-f]+$":
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# Child node
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