phy: rockchip-inno-usb2: add phy configurations for rk1808

RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.

Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu 2018-08-30 15:01:23 +08:00 committed by Tao Huang
parent 6870353515
commit 1c15193c9f

View File

@ -2138,6 +2138,59 @@ static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
#define ROCKCHIP_USB2PHY_DEV_PM NULL
#endif /* CONFIG_PM_SLEEP */
static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = {
{
.reg = 0x100,
.num_ports = 2,
.clkout_ctl = { 0x108, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
.bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
.bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
.iddig_output = { 0x0100, 10, 10, 0, 1 },
.iddig_en = { 0x0100, 9, 9, 0, 1 },
.idfall_det_en = { 0x0110, 5, 5, 0, 1 },
.idfall_det_st = { 0x0114, 5, 5, 0, 1 },
.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
.idrise_det_en = { 0x0110, 4, 4, 0, 1 },
.idrise_det_st = { 0x0114, 4, 4, 0, 1 },
.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
.ls_det_en = { 0x0110, 0, 0, 0, 1 },
.ls_det_st = { 0x0114, 0, 0, 0, 1 },
.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
.utmi_iddig = { 0x0120, 6, 6, 0, 1 },
.utmi_ls = { 0x0120, 5, 4, 0, 1 },
.vbus_det_en = { 0x001c, 15, 15, 1, 0 },
},
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
.ls_det_en = { 0x110, 1, 1, 0, 1 },
.ls_det_st = { 0x114, 1, 1, 0, 1 },
.ls_det_clr = { 0x118, 1, 1, 0, 1 },
.utmi_ls = { 0x120, 17, 16, 0, 1 },
.utmi_hstdet = { 0x120, 19, 19, 0, 1 }
}
},
.chg_det = {
.opmode = { 0x0100, 3, 0, 5, 1 },
.cp_det = { 0x0120, 24, 24, 0, 1 },
.dcp_det = { 0x0120, 23, 23, 0, 1 },
.dp_det = { 0x0120, 25, 25, 0, 1 },
.idm_sink_en = { 0x0108, 8, 8, 0, 1 },
.idp_sink_en = { 0x0108, 7, 7, 0, 1 },
.idp_src_en = { 0x0108, 9, 9, 0, 1 },
.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
},
},
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = {
{
.reg = 0x17c,
@ -2544,6 +2597,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
};
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,rk1808-usb2phy", .data = &rk1808_phy_cfgs },
{ .compatible = "rockchip,rk3128-usb2phy", .data = &rk312x_phy_cfgs },
{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },