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- The usual pile of cleanups all over the place
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commit
1bd2400fba
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@ -46,20 +46,7 @@ static __always_inline void native_write_cr3(unsigned long val)
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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#ifdef CONFIG_X86_32
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/*
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* This could fault if CR4 does not exist. Non-existent CR4
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* is functionally equivalent to CR4 == 0. Keep it simple and pretend
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* that CR4 == 0 on CPUs that don't have CR4.
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*/
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asm volatile("1: mov %%cr4, %0\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b)
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: "=r" (val) : "0" (0));
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#else
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/* CR4 always exists on x86_64. */
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asm volatile("mov %%cr4,%0" : "=r" (val));
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#endif
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return val;
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}
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@ -3,7 +3,6 @@
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#define _ASM_X86_STRING_64_H
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#ifdef __KERNEL__
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#include <linux/jump_label.h>
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/* Written 2002 by Andi Kleen */
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@ -1427,7 +1427,7 @@ static bool __init vulnerable_to_its(u64 x86_arch_cap_msr)
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return false;
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}
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static struct x86_cpu_id cpu_latest_microcode[] = {
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static const struct x86_cpu_id cpu_latest_microcode[] __initconst = {
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#include "microcode/intel-ucode-defs.h"
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{}
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};
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@ -51,11 +51,10 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
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/**
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* amd_set_mtrr - Set variable MTRR register on the local CPU.
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*
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* @reg The register to set.
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* @base The base address of the region.
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* @size The size of the region. If this is 0 the region is disabled.
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* @type The type of the region.
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* @reg: The register to set.
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* @base: The base address of the region.
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* @size: The size of the region. If this is 0 the region is disabled.
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* @type: The type of the region.
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*
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* Returns nothing.
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*/
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@ -1,9 +0,0 @@
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#ifndef __UM_REQUIRED_FEATURES_H
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#define __UM_REQUIRED_FEATURES_H
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/*
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* Nothing to see, just need something for the i386 and x86_64 asm
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* headers to include.
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*/
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#endif
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