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Merge branch 'pci/controller/mediatek-gen3'
- Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC types (Lorenzo Bianconi) - Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi) - Add DT and driver support for Airoha EN7581 PCIe controller (Lorenzo Bianconi) * pci/controller/mediatek-gen3: PCI: mediatek-gen3: Add Airoha EN7581 support PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581
This commit is contained in:
Bjorn Helgaas
commit
1bcf233154
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@ -53,6 +53,7 @@ properties:
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- mediatek,mt8195-pcie
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- const: mediatek,mt8192-pcie
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- const: mediatek,mt8192-pcie
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- const: airoha,en7581-pcie
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reg:
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maxItems: 1
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@ -76,20 +77,20 @@ properties:
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resets:
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minItems: 1
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maxItems: 2
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maxItems: 3
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reset-names:
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minItems: 1
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maxItems: 2
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maxItems: 3
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items:
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enum: [ phy, mac ]
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enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
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clocks:
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minItems: 4
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minItems: 1
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maxItems: 6
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clock-names:
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minItems: 4
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minItems: 1
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maxItems: 6
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assigned-clocks:
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@ -147,6 +148,9 @@ allOf:
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const: mediatek,mt8192-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pl_250m
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@ -155,6 +159,15 @@ allOf:
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- const: tl_32k
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- const: peri_26m
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- const: top_133m
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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- if:
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properties:
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compatible:
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@ -164,6 +177,9 @@ allOf:
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- mediatek,mt8195-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pl_250m
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@ -172,6 +188,15 @@ allOf:
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- const: tl_32k
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- const: peri_26m
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- const: peri_mem
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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- if:
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properties:
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compatible:
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@ -180,6 +205,9 @@ allOf:
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- mediatek,mt7986-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pl_250m
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@ -187,6 +215,36 @@ allOf:
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- const: peri_26m
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- const: top_133m
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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- if:
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properties:
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compatible:
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const: airoha,en7581-pcie
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: sys-ck
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resets:
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minItems: 3
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reset-names:
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items:
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- const: phy-lane0
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- const: phy-lane1
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- const: phy-lane2
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unevaluatedProperties: false
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examples:
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@ -196,7 +196,7 @@ config PCIE_MEDIATEK
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config PCIE_MEDIATEK_GEN3
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tristate "MediaTek Gen3 PCIe controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
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depends on PCI_MSI
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help
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Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
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@ -6,7 +6,9 @@
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* Author: Jianjun Wang <jianjun.wang@mediatek.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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@ -15,6 +17,8 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_device.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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@ -29,6 +33,12 @@
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#define PCI_CLASS(class) (class << 8)
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#define PCIE_RC_MODE BIT(0)
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#define PCIE_EQ_PRESET_01_REG 0x100
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#define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)
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#define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8)
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#define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16)
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#define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24)
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#define PCIE_CFGNUM_REG 0x140
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#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
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#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
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@ -68,6 +78,14 @@
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#define PCIE_MSI_SET_ENABLE_REG 0x190
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#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
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#define PCIE_PIPE4_PIE8_REG 0x338
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#define PCIE_K_FINETUNE_MAX GENMASK(5, 0)
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#define PCIE_K_FINETUNE_ERR GENMASK(7, 6)
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#define PCIE_K_PRESET_TO_USE GENMASK(18, 8)
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#define PCIE_K_PHYPARAM_QUERY BIT(19)
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#define PCIE_K_QUERY_TIMEOUT BIT(20)
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#define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21)
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#define PCIE_MSI_SET_BASE_REG 0xc00
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#define PCIE_MSI_SET_OFFSET 0x10
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#define PCIE_MSI_SET_STATUS_OFFSET 0x04
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@ -100,6 +118,26 @@
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#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
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#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
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#define MAX_NUM_PHY_RESETS 3
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/* Time in ms needed to complete PCIe reset on EN7581 SoC */
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#define PCIE_EN7581_RESET_TIME_MS 100
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struct mtk_gen3_pcie;
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/**
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* struct mtk_gen3_pcie_pdata - differentiate between host generations
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* @power_up: pcie power_up callback
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* @phy_resets: phy reset lines SoC data.
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*/
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struct mtk_gen3_pcie_pdata {
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int (*power_up)(struct mtk_gen3_pcie *pcie);
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struct {
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const char *id[MAX_NUM_PHY_RESETS];
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int num_resets;
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} phy_resets;
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};
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/**
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* struct mtk_msi_set - MSI information for each set
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* @base: IO mapped register base
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@ -118,7 +156,7 @@ struct mtk_msi_set {
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* @base: IO mapped register base
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* @reg_base: physical register base
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* @mac_reset: MAC reset control
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* @phy_reset: PHY reset control
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* @phy_resets: PHY reset controllers
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* @phy: PHY controller block
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* @clks: PCIe clocks
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* @num_clks: PCIe clocks count for this port
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@ -131,13 +169,14 @@ struct mtk_msi_set {
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* @msi_sets: MSI sets information
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* @lock: lock protecting IRQ bit map
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* @msi_irq_in_use: bit map for assigned MSI IRQ
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* @soc: pointer to SoC-dependent operations
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*/
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struct mtk_gen3_pcie {
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struct device *dev;
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void __iomem *base;
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phys_addr_t reg_base;
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struct reset_control *mac_reset;
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struct reset_control *phy_reset;
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struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS];
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struct phy *phy;
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struct clk_bulk_data *clks;
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int num_clks;
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@ -151,6 +190,8 @@ struct mtk_gen3_pcie {
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struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
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struct mutex lock;
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DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
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const struct mtk_gen3_pcie_pdata *soc;
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};
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/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
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@ -768,10 +809,10 @@ static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)
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static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
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{
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int i, ret, num_resets = pcie->soc->phy_resets.num_resets;
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *regs;
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int ret;
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regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
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if (!regs)
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@ -784,12 +825,12 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
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pcie->reg_base = regs->start;
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pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
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if (IS_ERR(pcie->phy_reset)) {
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ret = PTR_ERR(pcie->phy_reset);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to get PHY reset\n");
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for (i = 0; i < num_resets; i++)
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pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
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ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);
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if (ret) {
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dev_err(dev, "failed to get PHY bulk reset\n");
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return ret;
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}
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@ -820,13 +861,96 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
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return 0;
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}
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static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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int err;
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u32 val;
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|
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/*
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* Wait for the time needed to complete the bulk assert in
|
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* mtk_pcie_setup for EN7581 SoC.
|
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*/
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mdelay(PCIE_EN7581_RESET_TIME_MS);
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err = phy_init(pcie->phy);
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if (err) {
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dev_err(dev, "failed to initialize PHY\n");
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return err;
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}
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|
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err = phy_power_on(pcie->phy);
|
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if (err) {
|
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dev_err(dev, "failed to power on PHY\n");
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goto err_phy_on;
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}
|
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|
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err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
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if (err) {
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dev_err(dev, "failed to deassert PHYs\n");
|
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goto err_phy_deassert;
|
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}
|
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|
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/*
|
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* Wait for the time needed to complete the bulk de-assert above.
|
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* This time is specific for EN7581 SoC.
|
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*/
|
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mdelay(PCIE_EN7581_RESET_TIME_MS);
|
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|
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pm_runtime_enable(dev);
|
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pm_runtime_get_sync(dev);
|
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|
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err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
|
||||
if (err) {
|
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dev_err(dev, "failed to prepare clock\n");
|
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goto err_clk_prepare;
|
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}
|
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|
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val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
|
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FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
|
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FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
|
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FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41);
|
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writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG);
|
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|
||||
val = PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT |
|
||||
FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) |
|
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FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) |
|
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FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
|
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writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
|
||||
|
||||
err = clk_bulk_enable(pcie->num_clks, pcie->clks);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to prepare clock\n");
|
||||
goto err_clk_enable;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_enable:
|
||||
clk_bulk_unprepare(pcie->num_clks, pcie->clks);
|
||||
err_clk_prepare:
|
||||
pm_runtime_put_sync(dev);
|
||||
pm_runtime_disable(dev);
|
||||
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
err_phy_deassert:
|
||||
phy_power_off(pcie->phy);
|
||||
err_phy_on:
|
||||
phy_exit(pcie->phy);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
|
||||
{
|
||||
struct device *dev = pcie->dev;
|
||||
int err;
|
||||
|
||||
/* PHY power on and enable pipe clock */
|
||||
reset_control_deassert(pcie->phy_reset);
|
||||
err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to deassert PHYs\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = phy_init(pcie->phy);
|
||||
if (err) {
|
||||
|
|
@ -862,7 +986,7 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
|
|||
err_phy_on:
|
||||
phy_exit(pcie->phy);
|
||||
err_phy_init:
|
||||
reset_control_assert(pcie->phy_reset);
|
||||
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -877,7 +1001,7 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
|
|||
|
||||
phy_power_off(pcie->phy);
|
||||
phy_exit(pcie->phy);
|
||||
reset_control_assert(pcie->phy_reset);
|
||||
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
}
|
||||
|
||||
static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
|
||||
|
|
@ -888,16 +1012,22 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* Deassert the line in order to avoid unbalance in deassert_count
|
||||
* counter since the bulk is shared.
|
||||
*/
|
||||
reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
/*
|
||||
* The controller may have been left out of reset by the bootloader
|
||||
* so make sure that we get a clean start by asserting resets here.
|
||||
*/
|
||||
reset_control_assert(pcie->phy_reset);
|
||||
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
|
||||
|
||||
reset_control_assert(pcie->mac_reset);
|
||||
usleep_range(10, 20);
|
||||
|
||||
/* Don't touch the hardware registers before power up */
|
||||
err = mtk_pcie_power_up(pcie);
|
||||
err = pcie->soc->power_up(pcie);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -932,6 +1062,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
|
|||
pcie = pci_host_bridge_priv(host);
|
||||
|
||||
pcie->dev = dev;
|
||||
pcie->soc = device_get_match_data(dev);
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
err = mtk_pcie_setup(pcie);
|
||||
|
|
@ -1047,7 +1178,7 @@ static int mtk_pcie_resume_noirq(struct device *dev)
|
|||
struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
|
||||
int err;
|
||||
|
||||
err = mtk_pcie_power_up(pcie);
|
||||
err = pcie->soc->power_up(pcie);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -1067,8 +1198,27 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
|
|||
mtk_pcie_resume_noirq)
|
||||
};
|
||||
|
||||
static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
|
||||
.power_up = mtk_pcie_power_up,
|
||||
.phy_resets = {
|
||||
.id[0] = "phy",
|
||||
.num_resets = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {
|
||||
.power_up = mtk_pcie_en7581_power_up,
|
||||
.phy_resets = {
|
||||
.id[0] = "phy-lane0",
|
||||
.id[1] = "phy-lane1",
|
||||
.id[2] = "phy-lane2",
|
||||
.num_resets = 3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_pcie_of_match[] = {
|
||||
{ .compatible = "mediatek,mt8192-pcie" },
|
||||
{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
|
||||
{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user