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PCI/MSI: Switch to MSI descriptor locking to guard()
Convert the code to use the new guard(msi_descs_lock). No functional change intended. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/all/20250313130321.695027112@linutronix.de
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@ -53,10 +53,9 @@ void pci_disable_msi(struct pci_dev *dev)
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if (!pci_msi_enabled() || !dev || !dev->msi_enabled)
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return;
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msi_lock_descs(&dev->dev);
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guard(msi_descs_lock)(&dev->dev);
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pci_msi_shutdown(dev);
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pci_free_msi_irqs(dev);
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msi_unlock_descs(&dev->dev);
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}
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EXPORT_SYMBOL(pci_disable_msi);
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@ -196,10 +195,9 @@ void pci_disable_msix(struct pci_dev *dev)
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if (!pci_msi_enabled() || !dev || !dev->msix_enabled)
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return;
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msi_lock_descs(&dev->dev);
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guard(msi_descs_lock)(&dev->dev);
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pci_msix_shutdown(dev);
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pci_free_msi_irqs(dev);
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msi_unlock_descs(&dev->dev);
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}
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EXPORT_SYMBOL(pci_disable_msix);
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@ -336,41 +336,11 @@ static int msi_verify_entries(struct pci_dev *dev)
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return !entry ? 0 : -EIO;
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}
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/**
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* msi_capability_init - configure device's MSI capability structure
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* @dev: pointer to the pci_dev data structure of MSI device function
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* @nvec: number of interrupts to allocate
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* @affd: description of automatic IRQ affinity assignments (may be %NULL)
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*
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* Setup the MSI capability structure of the device with the requested
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* number of interrupts. A return value of zero indicates the successful
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* setup of an entry with the new MSI IRQ. A negative return value indicates
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* an error, and a positive return value indicates the number of interrupts
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* which could have been allocated.
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*/
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static int msi_capability_init(struct pci_dev *dev, int nvec,
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struct irq_affinity *affd)
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static int __msi_capability_init(struct pci_dev *dev, int nvec, struct irq_affinity_desc *masks)
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{
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struct irq_affinity_desc *masks = NULL;
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int ret = msi_setup_msi_desc(dev, nvec, masks);
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struct msi_desc *entry, desc;
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int ret;
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/* Reject multi-MSI early on irq domain enabled architectures */
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if (nvec > 1 && !pci_msi_domain_supports(dev, MSI_FLAG_MULTI_PCI_MSI, ALLOW_LEGACY))
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return 1;
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/*
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* Disable MSI during setup in the hardware, but mark it enabled
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* so that setup code can evaluate it.
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*/
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pci_msi_set_enable(dev, 0);
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dev->msi_enabled = 1;
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if (affd)
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masks = irq_create_affinity_masks(nvec, affd);
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msi_lock_descs(&dev->dev);
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ret = msi_setup_msi_desc(dev, nvec, masks);
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if (ret)
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goto fail;
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@ -399,19 +369,48 @@ static int msi_capability_init(struct pci_dev *dev, int nvec,
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pcibios_free_irq(dev);
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dev->irq = entry->irq;
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goto unlock;
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return 0;
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err:
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pci_msi_unmask(&desc, msi_multi_mask(&desc));
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pci_free_msi_irqs(dev);
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fail:
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dev->msi_enabled = 0;
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unlock:
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msi_unlock_descs(&dev->dev);
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kfree(masks);
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return ret;
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}
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/**
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* msi_capability_init - configure device's MSI capability structure
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* @dev: pointer to the pci_dev data structure of MSI device function
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* @nvec: number of interrupts to allocate
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* @affd: description of automatic IRQ affinity assignments (may be %NULL)
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*
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* Setup the MSI capability structure of the device with the requested
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* number of interrupts. A return value of zero indicates the successful
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* setup of an entry with the new MSI IRQ. A negative return value indicates
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* an error, and a positive return value indicates the number of interrupts
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* which could have been allocated.
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*/
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static int msi_capability_init(struct pci_dev *dev, int nvec,
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struct irq_affinity *affd)
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{
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/* Reject multi-MSI early on irq domain enabled architectures */
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if (nvec > 1 && !pci_msi_domain_supports(dev, MSI_FLAG_MULTI_PCI_MSI, ALLOW_LEGACY))
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return 1;
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/*
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* Disable MSI during setup in the hardware, but mark it enabled
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* so that setup code can evaluate it.
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*/
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pci_msi_set_enable(dev, 0);
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dev->msi_enabled = 1;
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struct irq_affinity_desc *masks __free(kfree) =
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affd ? irq_create_affinity_masks(nvec, affd) : NULL;
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guard(msi_descs_lock)(&dev->dev);
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return __msi_capability_init(dev, nvec, masks);
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}
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int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
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struct irq_affinity *affd)
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{
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@ -666,40 +665,41 @@ static void msix_mask_all(void __iomem *base, int tsize)
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writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
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}
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static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries,
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int nvec, struct irq_affinity *affd)
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static int __msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries,
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int nvec, struct irq_affinity_desc *masks)
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{
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struct irq_affinity_desc *masks = NULL;
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int ret;
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int ret = msix_setup_msi_descs(dev, entries, nvec, masks);
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if (affd)
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masks = irq_create_affinity_masks(nvec, affd);
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msi_lock_descs(&dev->dev);
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ret = msix_setup_msi_descs(dev, entries, nvec, masks);
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if (ret)
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goto out_free;
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goto fail;
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ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
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if (ret)
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goto out_free;
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goto fail;
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/* Check if all MSI entries honor device restrictions */
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ret = msi_verify_entries(dev);
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if (ret)
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goto out_free;
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goto fail;
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msix_update_entries(dev, entries);
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goto out_unlock;
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return 0;
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out_free:
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fail:
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pci_free_msi_irqs(dev);
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out_unlock:
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msi_unlock_descs(&dev->dev);
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kfree(masks);
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return ret;
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}
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static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries,
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int nvec, struct irq_affinity *affd)
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{
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struct irq_affinity_desc *masks __free(kfree) =
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affd ? irq_create_affinity_masks(nvec, affd) : NULL;
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guard(msi_descs_lock)(&dev->dev);
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return __msix_setup_interrupts(dev, entries, nvec, masks);
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}
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/**
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* msix_capability_init - configure device's MSI-X capability
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* @dev: pointer to the pci_dev data structure of MSI-X device function
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@ -871,13 +871,13 @@ void __pci_restore_msix_state(struct pci_dev *dev)
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write_msg = arch_restore_msi_irqs(dev);
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msi_lock_descs(&dev->dev);
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msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
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if (write_msg)
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__pci_write_msi_msg(entry, &entry->msg);
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pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
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scoped_guard (msi_descs_lock, &dev->dev) {
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msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
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if (write_msg)
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__pci_write_msi_msg(entry, &entry->msg);
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pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
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}
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}
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msi_unlock_descs(&dev->dev);
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pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
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}
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