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arm64: dts: qcom: msm8996: add blsp2_spi5 node

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Add the blsp2_spi5 SPI controller node together with its default and sleep
pinctrl states.

Signed-off-by: Christopher Obbard <christopher.obbard@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260508-wip-obbardc-msm8996-blsp2_spi4-v2-1-8b81a95b1ed7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Christopher Obbard 2026-05-08 03:30:06 +01:00 committed by Bjorn Andersson
parent 6a3568f938
commit 1ba506e643
1 changed files with 41 additions and 0 deletions
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41
arch/arm64/boot/dts/qcom/msm8996.dtsi
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@ -1632,6 +1632,30 @@ blsp2_i2c5_default: blsp2-i2c5-state {
/* Sleep state for BLSP2_I2C5 is missing.. */
blsp2_spi5_default: blsp2-spi5-default-state {
spi-pins {
pins = "gpio58", "gpio59", "gpio61";
function = "blsp_spi11";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio60";
function = "blsp_spi11";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp2_spi5_sleep: blsp2-spi5-sleep-state {
pins = "gpio58", "gpio59", "gpio60", "gpio61";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
cdc_reset_active: cdc-reset-active-state {
pins = "gpio64";
function = "gpio";
@ -3433,6 +3457,23 @@ blsp2_i2c5: i2c@75b9000 {
status = "disabled";
};
blsp2_spi5: spi@75b9000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x75b9000 0x600>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c6: i2c@75ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>;