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ASoC: codecs: aw88261: support changing sample rate and bit width
The aw88261 driver only worked with 32-bit 48kHz streams so far due to
the lack of a proper PLL initialization sequence. Fix by selecting all
the necessary PLL settings based on what was passed to us by the
hw_params/set_fmt ops. This replaces the strange downstream routine
that tries two divider modes in sequence.
Fixes: 028a2ae256 ("ASoC: codecs: Add aw88261 amplifier driver")
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5
Signed-off-by: Val Packett <val@packett.cool>
Link: https://patch.msgid.link/20260529200550.529719-2-val@packett.cool
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Val Packett
Mark Brown
parent
4549871118
commit
1b92b0673d
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@ -13,6 +13,7 @@
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <sound/soc.h>
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#include <sound/pcm_params.h>
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#include "aw88261.h"
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#include "aw88395/aw88395_data_type.h"
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#include "aw88395/aw88395_device.h"
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@ -158,7 +159,7 @@ static int aw88261_dev_get_iis_status(struct aw_device *aw_dev)
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return ret;
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}
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static int aw88261_dev_check_mode1_pll(struct aw_device *aw_dev)
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static int aw88261_dev_check_pll(struct aw_device *aw_dev)
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{
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int ret, i;
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@ -175,71 +176,48 @@ static int aw88261_dev_check_mode1_pll(struct aw_device *aw_dev)
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return -EPERM;
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}
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static int aw88261_dev_check_mode2_pll(struct aw_device *aw_dev)
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{
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unsigned int reg_val;
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int ret, i;
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ret = regmap_read(aw_dev->regmap, AW88261_PLLCTRL1_REG, ®_val);
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if (ret)
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return ret;
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reg_val &= (~AW88261_CCO_MUX_MASK);
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if (reg_val == AW88261_CCO_MUX_DIVIDED_VALUE) {
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dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
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return -EPERM;
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}
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/* change mode2 */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG,
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~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_DIVIDED_VALUE);
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if (ret)
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return ret;
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for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
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ret = aw88261_dev_get_iis_status(aw_dev);
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if (ret) {
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dev_err(aw_dev->dev, "mode2 iis signal check error");
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usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
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} else {
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break;
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}
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}
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/* change mode1 */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG,
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~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_BYPASS_VALUE);
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if (ret == 0) {
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usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
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for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) {
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ret = aw88261_dev_check_mode1_pll(aw_dev);
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if (ret) {
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dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
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usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
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} else {
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break;
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}
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}
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}
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return ret;
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}
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static int aw88261_dev_check_syspll(struct aw_device *aw_dev)
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static int aw88261_dev_configure_syspll(struct aw88261 *aw88261)
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{
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struct aw_device *aw_dev = aw88261->aw_pa;
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int ret;
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ret = aw88261_dev_check_mode1_pll(aw_dev);
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if (ret) {
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dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
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ret = aw88261_dev_check_mode2_pll(aw_dev);
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if (ret) {
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dev_err(aw_dev->dev, "mode2 check iis failed");
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return ret;
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}
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}
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/* PLL divider must be used for 8/16/32 kHz modes */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG,
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~AW88261_CCO_MUX_MASK, aw88261->cco_mux_value);
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if (ret)
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return ret;
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return ret;
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/* The word clock (WCK) defines the beginning of a frame */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_I2SCTRL1_REG,
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~AW88261_I2SSR_MASK, aw88261->sr_value);
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if (ret)
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return ret;
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/* The bit clock (BCK) defines the length of a frame */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_I2SCTRL1_REG,
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~AW88261_I2SBCK_MASK, aw88261->bck_value);
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if (ret)
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return ret;
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/* The logical frame size is the width of data for 1 slot */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_I2SCTRL1_REG,
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~AW88261_I2SFS_MASK, aw88261->fs_value);
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if (ret)
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return ret;
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/* The I2S interface mode (Philips standard, LSB/MSB justified) */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_I2SCTRL1_REG,
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~AW88261_I2SMD_MASK, aw88261->md_value);
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if (ret)
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return ret;
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/* The polarity of the bit clock (BCK) */
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ret = regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG,
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~AW88261_BCKINV_MASK, aw88261->bck_inv_value);
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if (ret)
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return ret;
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return aw88261_dev_check_pll(aw_dev);
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}
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static int aw88261_dev_check_sysst(struct aw_device *aw_dev)
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@ -558,7 +536,7 @@ static int aw88261_dev_start(struct aw88261 *aw88261)
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aw88261_dev_pwd(aw_dev, false);
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usleep_range(AW88261_2000_US, AW88261_2000_US + 10);
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ret = aw88261_dev_check_syspll(aw_dev);
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ret = aw88261_dev_configure_syspll(aw88261);
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if (ret) {
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dev_err(aw_dev->dev, "pll check failed cannot start");
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goto pll_check_fail;
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@ -712,6 +690,140 @@ static void aw88261_start(struct aw88261 *aw88261, bool sync_start)
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AW88261_START_WORK_DELAY_MS);
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}
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static int aw88261_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct snd_soc_component *component = dai->component;
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struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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aw88261->bck_inv_value = AW88261_BCKINV_NOT_INVERT_VALUE;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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aw88261->bck_inv_value = AW88261_BCKINV_INVERTED_VALUE;
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break;
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default:
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dev_err(aw88261->aw_pa->dev, "unsupported invert mode 0x%x\n",
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fmt & SND_SOC_DAIFMT_INV_MASK);
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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aw88261->md_value = AW88261_I2SMD_PHILIPS_STANDARD_VALUE;
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break;
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case SND_SOC_DAIFMT_MSB:
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aw88261->md_value = AW88261_I2SMD_MSB_JUSTIFIED_VALUE;
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break;
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case SND_SOC_DAIFMT_LSB:
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aw88261->md_value = AW88261_I2SMD_LSB_JUSTIFIED_VALUE;
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break;
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default:
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dev_err(aw88261->aw_pa->dev, "unsupported DAI format 0x%x\n",
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fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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}
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return 0;
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}
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static int aw88261_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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return 0;
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aw88261->cco_mux_value = AW88261_CCO_MUX_BYPASS_VALUE;
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switch (params_rate(params)) {
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case 8000:
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aw88261->sr_value = AW88261_I2SSR_8KHZ_VALUE;
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aw88261->cco_mux_value = AW88261_CCO_MUX_DIVIDED_VALUE;
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break;
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case 11025:
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aw88261->sr_value = AW88261_I2SSR_11P025KHZ_VALUE;
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break;
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case 12000:
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aw88261->sr_value = AW88261_I2SSR_12KHZ_VALUE;
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break;
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case 16000:
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aw88261->sr_value = AW88261_I2SSR_16KHZ_VALUE;
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aw88261->cco_mux_value = AW88261_CCO_MUX_DIVIDED_VALUE;
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break;
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case 22050:
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aw88261->sr_value = AW88261_I2SSR_22P05KHZ_VALUE;
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break;
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case 24000:
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aw88261->sr_value = AW88261_I2SSR_24KHZ_VALUE;
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break;
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case 32000:
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aw88261->sr_value = AW88261_I2SSR_32KHZ_VALUE;
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aw88261->cco_mux_value = AW88261_CCO_MUX_DIVIDED_VALUE;
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break;
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case 44100:
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aw88261->sr_value = AW88261_I2SSR_44P1KHZ_VALUE;
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break;
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case 48000:
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aw88261->sr_value = AW88261_I2SSR_48KHZ_VALUE;
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break;
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case 96000:
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aw88261->sr_value = AW88261_I2SSR_96KHZ_VALUE;
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break;
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case 192000:
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aw88261->sr_value = AW88261_I2SSR_192KHZ_VALUE;
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break;
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default:
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dev_err(aw88261->aw_pa->dev, "unsupported sample rate %d\n",
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params_rate(params));
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return -EINVAL;
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}
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switch (params_width(params)) {
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case 16:
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aw88261->fs_value = AW88261_I2SFS_16_BITS_VALUE;
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break;
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case 20:
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aw88261->fs_value = AW88261_I2SFS_20_BITS_VALUE;
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break;
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case 24:
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aw88261->fs_value = AW88261_I2SFS_24_BITS_VALUE;
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break;
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case 32:
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aw88261->fs_value = AW88261_I2SFS_32_BITS_VALUE;
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break;
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default:
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dev_err(aw88261->aw_pa->dev, "unsupported bit width %d\n",
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params_width(params));
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return -EINVAL;
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}
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switch (params_physical_width(params)) {
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case 16:
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aw88261->bck_value = AW88261_I2SBCK_32FS_VALUE;
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break;
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case 24:
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aw88261->bck_value = AW88261_I2SBCK_48FS_VALUE;
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break;
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case 32:
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aw88261->bck_value = AW88261_I2SBCK_64FS_VALUE;
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break;
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default:
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dev_err(aw88261->aw_pa->dev, "unsupported physical bit width %d\n",
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params_physical_width(params));
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops aw88261_dai_ops = {
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.set_fmt = aw88261_set_fmt,
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.hw_params = aw88261_hw_params,
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};
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static struct snd_soc_dai_driver aw88261_dai[] = {
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{
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.name = "aw88261-aif",
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@ -730,6 +842,7 @@ static struct snd_soc_dai_driver aw88261_dai[] = {
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.rates = AW88261_RATES,
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.formats = AW88261_FORMATS,
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},
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.ops = &aw88261_dai_ops,
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},
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};
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@ -1249,6 +1362,14 @@ static int aw88261_i2c_probe(struct i2c_client *i2c)
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if (!aw88261)
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return -ENOMEM;
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/* set defaults */
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aw88261->sr_value = AW88261_I2SSR_48KHZ_VALUE;
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aw88261->cco_mux_value = AW88261_CCO_MUX_BYPASS_VALUE;
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aw88261->fs_value = AW88261_I2SFS_24_BITS_VALUE;
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aw88261->bck_value = AW88261_I2SBCK_64FS_VALUE;
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aw88261->bck_inv_value = AW88261_BCKINV_NOT_INVERT_VALUE;
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aw88261->md_value = AW88261_I2SMD_PHILIPS_STANDARD_VALUE;
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mutex_init(&aw88261->lock);
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i2c_set_clientdata(i2c, aw88261);
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@ -116,6 +116,19 @@
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#define AW88261_VCALK_SHIFT (0)
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#define AW88261_VCALKL_SHIFT (0)
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#define AW88261_BCKINV_START_BIT (4)
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#define AW88261_BCKINV_BITS_LEN (1)
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#define AW88261_BCKINV_MASK \
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(~(((1<<AW88261_BCKINV_BITS_LEN)-1) << AW88261_BCKINV_START_BIT))
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#define AW88261_BCKINV_NOT_INVERT (0)
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#define AW88261_BCKINV_NOT_INVERT_VALUE \
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(AW88261_BCKINV_NOT_INVERT << AW88261_BCKINV_START_BIT)
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#define AW88261_BCKINV_INVERTED (1)
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#define AW88261_BCKINV_INVERTED_VALUE \
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(AW88261_BCKINV_INVERTED << AW88261_BCKINV_START_BIT)
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#define AW88261_AMPPD_START_BIT (1)
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#define AW88261_AMPPD_BITS_LEN (1)
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#define AW88261_AMPPD_MASK \
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@ -264,7 +277,98 @@
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#define AW88261_I2STXEN_ENABLE_VALUE \
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(AW88261_I2STXEN_ENABLE << AW88261_I2STXEN_START_BIT)
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#define AW88261_CCO_MUX_START_BIT (14)
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#define AW88261_I2SMD_START_BIT (8)
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#define AW88261_I2SMD_BITS_LEN (2)
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#define AW88261_I2SMD_MASK \
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(~(((1<<AW88261_I2SMD_BITS_LEN)-1) << AW88261_I2SMD_START_BIT))
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#define AW88261_I2SMD_PHILIPS_STANDARD (0)
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#define AW88261_I2SMD_PHILIPS_STANDARD_VALUE \
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(AW88261_I2SMD_PHILIPS_STANDARD << AW88261_I2SMD_START_BIT)
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#define AW88261_I2SMD_MSB_JUSTIFIED (1)
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#define AW88261_I2SMD_MSB_JUSTIFIED_VALUE \
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(AW88261_I2SMD_MSB_JUSTIFIED << AW88261_I2SMD_START_BIT)
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#define AW88261_I2SMD_LSB_JUSTIFIED (2)
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#define AW88261_I2SMD_LSB_JUSTIFIED_VALUE \
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(AW88261_I2SMD_LSB_JUSTIFIED << AW88261_I2SMD_START_BIT)
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#define AW88261_I2SFS_START_BIT (6)
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#define AW88261_I2SFS_BITS_LEN (2)
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#define AW88261_I2SFS_MASK \
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(~(((1<<AW88261_I2SFS_BITS_LEN)-1)<<AW88261_I2SFS_START_BIT))
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#define AW88261_I2SFS_16_BITS (0)
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#define AW88261_I2SFS_16_BITS_VALUE \
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(AW88261_I2SFS_16_BITS << AW88261_I2SFS_START_BIT)
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#define AW88261_I2SFS_20_BITS (1)
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#define AW88261_I2SFS_20_BITS_VALUE \
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(AW88261_I2SFS_20_BITS << AW88261_I2SFS_START_BIT)
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#define AW88261_I2SFS_24_BITS (2)
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#define AW88261_I2SFS_24_BITS_VALUE \
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(AW88261_I2SFS_24_BITS << AW88261_I2SFS_START_BIT)
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#define AW88261_I2SFS_32_BITS (3)
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#define AW88261_I2SFS_32_BITS_VALUE \
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(AW88261_I2SFS_32_BITS << AW88261_I2SFS_START_BIT)
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#define AW88261_I2SBCK_START_BIT (4)
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#define AW88261_I2SBCK_BITS_LEN (2)
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#define AW88261_I2SBCK_MASK \
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(~(((1<<AW88261_I2SBCK_BITS_LEN)-1) << AW88261_I2SBCK_START_BIT))
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#define AW88261_I2SBCK_32FS (0)
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#define AW88261_I2SBCK_32FS_VALUE \
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(AW88261_I2SBCK_32FS << AW88261_I2SBCK_START_BIT)
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#define AW88261_I2SBCK_48FS (1)
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#define AW88261_I2SBCK_48FS_VALUE \
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(AW88261_I2SBCK_48FS << AW88261_I2SBCK_START_BIT)
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#define AW88261_I2SBCK_64FS (2)
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#define AW88261_I2SBCK_64FS_VALUE \
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(AW88261_I2SBCK_64FS << AW88261_I2SBCK_START_BIT)
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#define AW88261_I2SSR_START_BIT (0)
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#define AW88261_I2SSR_BITS_LEN (4)
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#define AW88261_I2SSR_MASK \
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(~(((1<<AW88261_I2SSR_BITS_LEN)-1) << AW88261_I2SSR_START_BIT))
|
||||
|
||||
#define AW88261_I2SSR_8KHZ (0)
|
||||
#define AW88261_I2SSR_8KHZ_VALUE \
|
||||
(AW88261_I2SSR_8KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_11P025KHZ (1)
|
||||
#define AW88261_I2SSR_11P025KHZ_VALUE \
|
||||
(AW88261_I2SSR_11P025KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_12KHZ (2)
|
||||
#define AW88261_I2SSR_12KHZ_VALUE \
|
||||
(AW88261_I2SSR_12KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_16KHZ (3)
|
||||
#define AW88261_I2SSR_16KHZ_VALUE \
|
||||
(AW88261_I2SSR_16KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_22P05KHZ (4)
|
||||
#define AW88261_I2SSR_22P05KHZ_VALUE \
|
||||
(AW88261_I2SSR_22P05KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_24KHZ (5)
|
||||
#define AW88261_I2SSR_24KHZ_VALUE \
|
||||
(AW88261_I2SSR_24KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_32KHZ (6)
|
||||
#define AW88261_I2SSR_32KHZ_VALUE \
|
||||
(AW88261_I2SSR_32KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_44P1KHZ (7)
|
||||
#define AW88261_I2SSR_44P1KHZ_VALUE \
|
||||
(AW88261_I2SSR_44P1KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_48KHZ (8)
|
||||
#define AW88261_I2SSR_48KHZ_VALUE \
|
||||
(AW88261_I2SSR_48KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_96KHZ (9)
|
||||
#define AW88261_I2SSR_96KHZ_VALUE \
|
||||
(AW88261_I2SSR_96KHZ << AW88261_I2SSR_START_BIT)
|
||||
#define AW88261_I2SSR_192KHZ (10)
|
||||
#define AW88261_I2SSR_192KHZ_VALUE \
|
||||
(AW88261_I2SSR_192KHZ << AW88261_I2SSR_START_BIT)
|
||||
|
||||
#define AW88261_CCO_MUX_START_BIT (6)
|
||||
#define AW88261_CCO_MUX_BITS_LEN (1)
|
||||
#define AW88261_CCO_MUX_MASK \
|
||||
(~(((1<<AW88261_CCO_MUX_BITS_LEN)-1) << AW88261_CCO_MUX_START_BIT))
|
||||
|
|
@ -370,7 +474,10 @@
|
|||
#define AW88261_START_RETRIES (5)
|
||||
#define AW88261_START_WORK_DELAY_MS (0)
|
||||
|
||||
/* NOTE: 192000 has a reg value donwstream but not listed in datasheet */
|
||||
#define AW88261_RATES (SNDRV_PCM_RATE_8000_48000 | \
|
||||
SNDRV_PCM_RATE_12000 | \
|
||||
SNDRV_PCM_RATE_24000 | \
|
||||
SNDRV_PCM_RATE_96000)
|
||||
#define AW88261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
|
|
@ -451,6 +558,13 @@ struct aw88261 {
|
|||
unsigned int mute_st;
|
||||
unsigned int amppd_st;
|
||||
|
||||
unsigned int sr_value;
|
||||
unsigned int cco_mux_value;
|
||||
unsigned int fs_value;
|
||||
unsigned int bck_value;
|
||||
unsigned int bck_inv_value;
|
||||
unsigned int md_value;
|
||||
|
||||
bool phase_sync;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user