From 1b3c392bd655af31a414fc82382cec13e090a997 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 20 May 2026 12:51:40 +0100 Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2L,G2LC} (r9a07g044) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260520115144.60067-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 873b52b168bc..f40315a707d1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1174,6 +1174,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G044_SDHI0_IXRST>; power-domains = <&cpg>; status = "disabled"; @@ -1190,6 +1191,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <133333333>; resets = <&cpg R9A07G044_SDHI1_IXRST>; power-domains = <&cpg>; status = "disabled";