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drm/i915: move memory frequency detection to intel_dram.c
The memory frequency detection is a bit spread out here and there. Consolidate to intel_dram.c. v2: - Remove inaccurate comment (Ville) - Call detect_mem_freq() unconditionally (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8a862eeca8b42a98e04b3c52637851d33531abb6.1676317696.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
f9dfa87c43
commit
1b2146de7c
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@ -1677,7 +1677,6 @@ static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
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static void vlv_rps_init(struct intel_rps *rps)
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{
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struct drm_i915_private *i915 = rps_to_i915(rps);
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u32 val;
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vlv_iosf_sb_get(i915,
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BIT(VLV_IOSF_SB_PUNIT) |
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@ -1686,21 +1685,6 @@ static void vlv_rps_init(struct intel_rps *rps)
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vlv_init_gpll_ref_freq(rps);
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val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
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switch ((val >> 6) & 3) {
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case 0:
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case 1:
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i915->mem_freq = 800;
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break;
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case 2:
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i915->mem_freq = 1066;
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break;
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case 3:
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i915->mem_freq = 1333;
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break;
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}
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drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
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rps->max_freq = vlv_rps_max_freq(rps);
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rps->rp0_freq = rps->max_freq;
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drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
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@ -1727,7 +1711,6 @@ static void vlv_rps_init(struct intel_rps *rps)
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static void chv_rps_init(struct intel_rps *rps)
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{
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struct drm_i915_private *i915 = rps_to_i915(rps);
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u32 val;
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vlv_iosf_sb_get(i915,
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BIT(VLV_IOSF_SB_PUNIT) |
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@ -1736,18 +1719,6 @@ static void chv_rps_init(struct intel_rps *rps)
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vlv_init_gpll_ref_freq(rps);
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val = vlv_cck_read(i915, CCK_FUSE_REG);
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switch ((val >> 2) & 0x7) {
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case 3:
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i915->mem_freq = 2000;
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break;
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default:
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i915->mem_freq = 1600;
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break;
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}
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drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
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rps->max_freq = chv_rps_max_freq(rps);
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rps->rp0_freq = rps->max_freq;
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drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
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@ -131,101 +131,6 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
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PWM1_GATING_DIS | PWM2_GATING_DIS);
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}
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static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
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{
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u32 tmp;
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tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
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switch (tmp & CLKCFG_FSB_MASK) {
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case CLKCFG_FSB_533:
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dev_priv->fsb_freq = 533; /* 133*4 */
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break;
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case CLKCFG_FSB_800:
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dev_priv->fsb_freq = 800; /* 200*4 */
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break;
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case CLKCFG_FSB_667:
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dev_priv->fsb_freq = 667; /* 167*4 */
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break;
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case CLKCFG_FSB_400:
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dev_priv->fsb_freq = 400; /* 100*4 */
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break;
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}
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switch (tmp & CLKCFG_MEM_MASK) {
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case CLKCFG_MEM_533:
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dev_priv->mem_freq = 533;
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break;
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case CLKCFG_MEM_667:
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dev_priv->mem_freq = 667;
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break;
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case CLKCFG_MEM_800:
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dev_priv->mem_freq = 800;
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break;
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}
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/* detect pineview DDR3 setting */
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tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
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dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
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}
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static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
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{
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u16 ddrpll, csipll;
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ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
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csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
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switch (ddrpll & 0xff) {
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case 0xc:
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dev_priv->mem_freq = 800;
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break;
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case 0x10:
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dev_priv->mem_freq = 1066;
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break;
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case 0x14:
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dev_priv->mem_freq = 1333;
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break;
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case 0x18:
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dev_priv->mem_freq = 1600;
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break;
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default:
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drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
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ddrpll & 0xff);
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dev_priv->mem_freq = 0;
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break;
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}
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switch (csipll & 0x3ff) {
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case 0x00c:
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dev_priv->fsb_freq = 3200;
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break;
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case 0x00e:
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dev_priv->fsb_freq = 3733;
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break;
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case 0x010:
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dev_priv->fsb_freq = 4266;
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break;
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case 0x012:
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dev_priv->fsb_freq = 4800;
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break;
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case 0x014:
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dev_priv->fsb_freq = 5333;
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break;
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case 0x016:
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dev_priv->fsb_freq = 5866;
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break;
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case 0x018:
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dev_priv->fsb_freq = 6400;
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break;
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default:
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drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
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csipll & 0x3ff);
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dev_priv->fsb_freq = 0;
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break;
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}
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}
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static const struct cxsr_latency cxsr_latency_table[] = {
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{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
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{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
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@ -4893,12 +4798,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
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return;
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}
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/* For cxsr */
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if (IS_PINEVIEW(dev_priv))
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pnv_get_mem_freq(dev_priv);
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else if (GRAPHICS_VER(dev_priv) == 5)
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ilk_get_mem_freq(dev_priv);
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/* For FIFO watermark updates */
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if (HAS_PCH_SPLIT(dev_priv)) {
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ilk_setup_wm_latency(dev_priv);
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@ -10,6 +10,7 @@
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#include "intel_dram.h"
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#include "intel_mchbar_regs.h"
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#include "intel_pcode.h"
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#include "vlv_sideband.h"
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struct dram_dimm_info {
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u16 size;
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@ -42,6 +43,155 @@ static const char *intel_dram_type_str(enum intel_dram_type type)
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#undef DRAM_TYPE_STR
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static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
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{
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u32 tmp;
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tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
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switch (tmp & CLKCFG_FSB_MASK) {
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case CLKCFG_FSB_533:
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dev_priv->fsb_freq = 533; /* 133*4 */
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break;
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case CLKCFG_FSB_800:
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dev_priv->fsb_freq = 800; /* 200*4 */
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break;
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case CLKCFG_FSB_667:
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dev_priv->fsb_freq = 667; /* 167*4 */
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break;
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case CLKCFG_FSB_400:
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dev_priv->fsb_freq = 400; /* 100*4 */
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break;
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}
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switch (tmp & CLKCFG_MEM_MASK) {
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case CLKCFG_MEM_533:
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dev_priv->mem_freq = 533;
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break;
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case CLKCFG_MEM_667:
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dev_priv->mem_freq = 667;
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break;
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case CLKCFG_MEM_800:
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dev_priv->mem_freq = 800;
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break;
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}
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/* detect pineview DDR3 setting */
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tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
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dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
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}
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static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
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{
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u16 ddrpll, csipll;
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ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
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switch (ddrpll & 0xff) {
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case 0xc:
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dev_priv->mem_freq = 800;
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break;
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case 0x10:
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dev_priv->mem_freq = 1066;
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break;
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case 0x14:
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dev_priv->mem_freq = 1333;
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break;
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case 0x18:
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dev_priv->mem_freq = 1600;
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break;
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default:
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drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
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ddrpll & 0xff);
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dev_priv->mem_freq = 0;
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break;
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}
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csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
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switch (csipll & 0x3ff) {
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case 0x00c:
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dev_priv->fsb_freq = 3200;
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break;
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case 0x00e:
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dev_priv->fsb_freq = 3733;
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break;
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case 0x010:
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dev_priv->fsb_freq = 4266;
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break;
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case 0x012:
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dev_priv->fsb_freq = 4800;
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break;
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case 0x014:
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dev_priv->fsb_freq = 5333;
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break;
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case 0x016:
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dev_priv->fsb_freq = 5866;
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break;
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case 0x018:
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dev_priv->fsb_freq = 6400;
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break;
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default:
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drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
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csipll & 0x3ff);
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dev_priv->fsb_freq = 0;
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break;
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}
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}
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static void chv_detect_mem_freq(struct drm_i915_private *i915)
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{
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u32 val;
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
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val = vlv_cck_read(i915, CCK_FUSE_REG);
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
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switch ((val >> 2) & 0x7) {
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case 3:
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i915->mem_freq = 2000;
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break;
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default:
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i915->mem_freq = 1600;
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break;
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}
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}
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static void vlv_detect_mem_freq(struct drm_i915_private *i915)
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{
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u32 val;
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vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
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val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
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vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
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switch ((val >> 6) & 3) {
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case 0:
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case 1:
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i915->mem_freq = 800;
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break;
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case 2:
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i915->mem_freq = 1066;
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break;
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case 3:
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i915->mem_freq = 1333;
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break;
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}
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}
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static void detect_mem_freq(struct drm_i915_private *i915)
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{
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if (IS_PINEVIEW(i915))
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pnv_detect_mem_freq(i915);
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else if (GRAPHICS_VER(i915) == 5)
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ilk_detect_mem_freq(i915);
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else if (IS_CHERRYVIEW(i915))
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chv_detect_mem_freq(i915);
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else if (IS_VALLEYVIEW(i915))
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vlv_detect_mem_freq(i915);
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if (i915->mem_freq)
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drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
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}
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static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
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{
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return dimm->ranks * 64 / (dimm->width ?: 1);
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@ -507,6 +657,8 @@ void intel_dram_detect(struct drm_i915_private *i915)
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struct dram_info *dram_info = &i915->dram_info;
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int ret;
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detect_mem_freq(i915);
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if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
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return;
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