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drm/panel: himax-hx83102: support Waveshare 12.3" DSI panel
Add support for the Waveshare 12.3" DSI TOUCH-A panel. According to the vendor driver, it uses different mode_flags, so let the panel descriptions override driver-wide defaults. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Dmitry Baryshkov
parent
a8c56e00c6
commit
1af0feaca1
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@ -29,11 +29,14 @@
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#define HX83102_UNKNOWN_B8 0xb8
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#define HX83102_SETEXTC 0xb9
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#define HX83102_SETMIPI 0xba
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#define HX83102_UNKNOWN_BB 0xbb
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#define HX83102_SETVDC 0xbc
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#define HX83102_SETBANK 0xbd
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#define HX83102_UNKNOWN_BE 0xbe
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#define HX83102_SETPTBA 0xbf
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#define HX83102_SETSTBA 0xc0
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#define HX83102_UNKNOWN_C2 0xc2
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#define HX83102_UNKNOWN_C6 0xc6
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#define HX83102_SETTCON 0xc7
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#define HX83102_SETRAMDMY 0xc8
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#define HX83102_SETPWM 0xc9
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@ -78,6 +81,7 @@ struct hx83102_panel_desc {
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} size;
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bool has_backlight;
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unsigned long mode_flags;
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int (*init)(struct hx83102 *ctx);
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};
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@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)
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return dsi_ctx.accum_err;
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}
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/* This is HX83102-E, assuming commands are the same as the normal HX83102 */
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static int waveshare_12_3_a_init(struct hx83102 *ctx)
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{
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,
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0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,
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0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,
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0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,
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0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,
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0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,
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0x01, 0x58, 0x00, 0xff, 0x00, 0xff);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
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0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,
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0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,
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0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,
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0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,
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0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,
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0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,
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0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,
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0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,
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0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,
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0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,
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0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
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0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,
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0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,
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0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,
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0x08, 0x00, 0x63, 0x63);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,
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0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,
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0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,
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0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,
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0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,
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0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,
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0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
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0x98, 0x98, 0x98, 0x98);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,
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0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
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0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,
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0x2a, 0xaa, 0xaa, 0xaa);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
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0xaa, 0xaa);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
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0xff, 0xff, 0xff, 0xff,
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0xff, 0xf0, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xf0);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
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return dsi_ctx.accum_err;
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};
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static const struct drm_display_mode starry_mode = {
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.clock = 162680,
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.hdisplay = 1200,
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@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {
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.init = holitech_htf065h045_init,
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};
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static const struct drm_display_mode waveshare_12_3_a_mode = {
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.clock = 95000,
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.hdisplay = 720,
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.hsync_start = 720 + 10,
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.hsync_end = 720 + 10 + 10,
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.htotal = 720 + 10 + 10 + 12,
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.vdisplay = 1920,
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.vsync_start = 1920 + 64,
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.vsync_end = 1920 + 64 + 18,
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.vtotal = 1920 + 64 + 18 + 4,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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};
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static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {
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.modes = &waveshare_12_3_a_mode,
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.size = {
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.width_mm = 109,
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.height_mm = 292,
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},
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.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
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.init = waveshare_12_3_a_init,
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};
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static int hx83102_enable(struct drm_panel *panel)
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{
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msleep(130);
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@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)
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desc = of_device_get_match_data(&dsi->dev);
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dsi->lanes = 4;
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dsi->format = MIPI_DSI_FMT_RGB888;
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dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
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MIPI_DSI_MODE_LPM;
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if (desc->mode_flags)
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dsi->mode_flags = desc->mode_flags;
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else
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dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
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MIPI_DSI_MODE_LPM;
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ctx->desc = desc;
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ctx->dsi = dsi;
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ret = hx83102_panel_add(ctx);
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@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {
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{ .compatible = "holitech,htf065h045",
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.data = &holitech_htf065h045_desc
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},
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{ .compatible = "waveshare,12.3-dsi-touch-a",
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.data = &waveshare_12_3_inch_a_desc
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, hx83102_of_match);
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