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spi: stm32: fix Overrun issue at < 8bpw
When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. To achieve a safe suspension, we need to ensure that each word must be at least 8 SPI clock cycles long. That's why, if bpw is less than 8 bits, we need to use midi to reach 8 SPI clock cycles at least. This will ensure that each word achieve safe suspension and prevent overrun condition. Signed-off-by: Deepak Kumar <deepak.kumar01@st.com> Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Link: https://patch.msgid.link/20251218-stm32-spi-enhancements-v2-2-3b69901ca9fe@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1906,11 +1906,12 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, struct spi_transfer
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cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
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if ((len > 1) && (spi->cur_midi > 0)) {
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u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
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u32 midi = min_t(u32,
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DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
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FIELD_GET(STM32H7_SPI_CFG2_MIDI,
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STM32H7_SPI_CFG2_MIDI));
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u32 midi = DIV_ROUND_UP(spi->cur_midi, sck_period_ns);
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if ((spi->cur_bpw + midi) < 8)
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midi = 8 - spi->cur_bpw;
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midi = min_t(u32, midi, FIELD_MAX(STM32H7_SPI_CFG2_MIDI));
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dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
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sck_period_ns, midi, midi * sck_period_ns);
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