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clk: rockchip: rk3308: Remove the reduplicative dclk_vop_frac

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Fixes: 0ee785bb30 ("clk: rockchip: Add supprot to limit input rate for fractional divider")
Change-Id: Ifd387f4dd2cdddedda4cb65f36806260eb3e03ef
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2019-04-17 11:35:24 +08:00 committed by Tao Huang
parent fa98363309
commit 1aae5d1eed
1 changed files with 0 additions and 4 deletions
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4
drivers/clk/rockchip/clk-rk3308.c
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@ -465,10 +465,6 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, 0),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),