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drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Remove this driver's HIWORD_UPDATE macro, and replace instances of it with either FIELD_PREP_WM16 or FIELD_PREP_WM16_CONST, depending on whether they're in an initializer. This gives us better error checking, which already saved me some trouble during this refactor. The driver's HIWORD_UPDATE macro doesn't shift up the value, but expects a pre-shifted value. Meanwhile, FIELD_PREP_WM16 and FIELD_PREP_WM16_CONST will shift the value for us, based on the given mask. So a few things that used to be a HIWORD_UPDATE(VERY_LONG_FOO, VERY_LONG_FOO) are now a somewhat more pleasant FIELD_PREP_WM16(VERY_LONG_FOO, 1). There are some non-trivial refactors here. A few literals needed a UL suffix added to stop them from unintentionally overflowing as a signed long. To make sure all of these cases are caught, and not just the ones where the FIELD_PREP_WM16* macros use such a value as a mask, just mark every literal that's used as a mask as unsigned. Non-contiguous masks also have to be split into multiple FIELD_PREP_WM16* instances, as the macro's checks and shifting logic rely on contiguous masks. This is compile-tested only. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
This commit is contained in:
Nicolas Frattaroli
Yury Norov
parent
48d47732c2
commit
1a99efa3a5
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@ -7,6 +7,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/hw_bitfield.h>
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#include <linux/iopoll.h>
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#include <linux/math64.h>
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#include <linux/mfd/syscon.h>
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@ -148,7 +149,7 @@
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#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
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#define PX30_GRF_PD_VO_CON1 0x0438
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#define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
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#define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7)
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#define PX30_DSI_FORCERXMODE BIT(6)
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#define PX30_DSI_TURNDISABLE BIT(5)
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#define PX30_DSI_LCDC_SEL BIT(0)
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@ -167,16 +168,16 @@
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#define RK3399_DSI1_LCDC_SEL BIT(4)
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#define RK3399_GRF_SOC_CON22 0x6258
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#define RK3399_DSI0_TURNREQUEST (0xf << 12)
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#define RK3399_DSI0_TURNDISABLE (0xf << 8)
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#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
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#define RK3399_DSI0_FORCERXMODE (0xf << 0)
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#define RK3399_DSI0_TURNREQUEST (0xfUL << 12)
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#define RK3399_DSI0_TURNDISABLE (0xfUL << 8)
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#define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4)
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#define RK3399_DSI0_FORCERXMODE (0xfUL << 0)
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#define RK3399_GRF_SOC_CON23 0x625c
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#define RK3399_DSI1_TURNDISABLE (0xf << 12)
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#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
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#define RK3399_DSI1_FORCERXMODE (0xf << 4)
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#define RK3399_DSI1_ENABLE (0xf << 0)
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#define RK3399_DSI1_TURNDISABLE (0xfUL << 12)
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#define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8)
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#define RK3399_DSI1_FORCERXMODE (0xfUL << 4)
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#define RK3399_DSI1_ENABLE (0xfUL << 0)
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#define RK3399_GRF_SOC_CON24 0x6260
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#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
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@ -186,8 +187,8 @@
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#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)
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#define RK3568_GRF_VO_CON2 0x0368
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#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
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#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4)
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#define RK3568_DSI0_SKEWCALHS (0x1fUL << 11)
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#define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4)
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#define RK3568_DSI0_TURNDISABLE BIT(2)
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#define RK3568_DSI0_FORCERXMODE BIT(0)
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@ -197,18 +198,16 @@
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* come from. Name GRF_VO_CON3 is assumed.
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*/
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#define RK3568_GRF_VO_CON3 0x36c
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#define RK3568_DSI1_SKEWCALHS (0x1f << 11)
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#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4)
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#define RK3568_DSI1_SKEWCALHS (0x1fUL << 11)
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#define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4)
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#define RK3568_DSI1_TURNDISABLE BIT(2)
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#define RK3568_DSI1_FORCERXMODE BIT(0)
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#define RV1126_GRF_DSIPHY_CON 0x10220
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#define RV1126_DSI_FORCETXSTOPMODE (0xf << 4)
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#define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4)
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#define RV1126_DSI_TURNDISABLE BIT(2)
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#define RV1126_DSI_FORCERXMODE BIT(0)
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#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
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enum {
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DW_DSI_USAGE_IDLE,
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DW_DSI_USAGE_DSI,
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@ -1484,14 +1483,13 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
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{
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.reg = 0xff450000,
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.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
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.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
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PX30_DSI_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1),
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.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
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.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
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PX30_DSI_FORCERXMODE |
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PX30_DSI_FORCETXSTOPMODE),
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.lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE |
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PX30_DSI_FORCERXMODE |
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PX30_DSI_FORCETXSTOPMODE), 0),
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.max_data_lanes = 4,
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},
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@ -1502,9 +1500,9 @@ static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {
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{
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.reg = 0x10110000,
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.lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,
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.lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |
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RK3128_DSI_FORCERXMODE |
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RK3128_DSI_FORCETXSTOPMODE),
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.lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE |
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RK3128_DSI_FORCERXMODE |
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RK3128_DSI_FORCETXSTOPMODE), 0),
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.max_data_lanes = 4,
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},
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{ /* sentinel */ }
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@ -1514,16 +1512,16 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
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{
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.reg = 0xff960000,
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.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
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.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1),
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.max_data_lanes = 4,
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},
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{
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.reg = 0xff964000,
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.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
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.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1),
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.max_data_lanes = 4,
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},
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@ -1539,13 +1537,13 @@ static int rk3399_dphy_tx1rx1_init(struct phy *phy)
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* Assume ISP0 is supplied by the RX0 dphy.
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*/
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
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FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
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FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
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FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
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FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
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return 0;
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}
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@ -1559,21 +1557,20 @@ static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
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usleep_range(100, 150);
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
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FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
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FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
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FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
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FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0));
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/* Disable lane turn around, which is ignored in receive mode */
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
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HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
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FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0));
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
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RK3399_DSI1_TURNDISABLE));
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FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf));
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usleep_range(100, 150);
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dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
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@ -1581,8 +1578,8 @@ static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
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/* Enable dphy lanes */
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
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RK3399_DSI1_ENABLE));
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FIELD_PREP_WM16(RK3399_DSI1_ENABLE,
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GENMASK(dsi->dphy_config.lanes - 1, 0)));
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usleep_range(100, 150);
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@ -1594,7 +1591,7 @@ static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
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struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
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regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
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HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
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FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));
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return 0;
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}
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@ -1603,15 +1600,14 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
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{
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.reg = 0xff960000,
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.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
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.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
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RK3399_DSI0_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1),
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.lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
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.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
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RK3399_DSI0_TURNDISABLE |
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RK3399_DSI0_FORCETXSTOPMODE |
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RK3399_DSI0_FORCERXMODE),
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.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST |
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RK3399_DSI0_TURNDISABLE |
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RK3399_DSI0_FORCETXSTOPMODE |
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RK3399_DSI0_FORCERXMODE), 0),
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.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
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.max_data_lanes = 4,
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@ -1619,25 +1615,23 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
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{
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.reg = 0xff968000,
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.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
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.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
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.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
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RK3399_DSI1_LCDC_SEL),
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.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0),
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.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1),
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.lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
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.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
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RK3399_DSI1_FORCETXSTOPMODE |
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RK3399_DSI1_FORCERXMODE |
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RK3399_DSI1_ENABLE),
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.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE |
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RK3399_DSI1_FORCETXSTOPMODE |
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RK3399_DSI1_FORCERXMODE |
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RK3399_DSI1_ENABLE), 0),
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.lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
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.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
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RK3399_TXRX_ENABLECLK,
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RK3399_TXRX_MASTERSLAVEZ |
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RK3399_TXRX_ENABLECLK |
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RK3399_TXRX_BASEDIR),
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.lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) |
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FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) |
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FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)),
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.enable_grf_reg = RK3399_GRF_SOC_CON23,
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.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
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.enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
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.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
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.max_data_lanes = 4,
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@ -1653,19 +1647,19 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
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{
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.reg = 0xfe060000,
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.lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
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.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
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RK3568_DSI0_FORCETXSTOPMODE |
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RK3568_DSI0_TURNDISABLE |
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RK3568_DSI0_FORCERXMODE),
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.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)),
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.max_data_lanes = 4,
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},
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{
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.reg = 0xfe070000,
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.lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
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.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
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RK3568_DSI1_FORCETXSTOPMODE |
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RK3568_DSI1_TURNDISABLE |
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RK3568_DSI1_FORCERXMODE),
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.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) |
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FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)),
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.max_data_lanes = 4,
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},
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{ /* sentinel */ }
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@ -1675,9 +1669,9 @@ static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {
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{
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.reg = 0xffb30000,
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.lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,
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.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |
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RV1126_DSI_FORCERXMODE |
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RV1126_DSI_FORCETXSTOPMODE),
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.lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) |
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FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) |
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FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)),
|
||||
.max_data_lanes = 4,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user