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https://github.com/torvalds/linux.git
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ASoC: Fix sdw_utils calling wrong codec init callbacks
Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>: This series fixes a problem with soc_sdw_utils.c calling the wrong codec init callbacks, because it assumed that the DAI name could be used to uniquely identify the codec. This isn't the case, especially on SDCA which is a generic driver for many parts. The first patch is needed to add a missing export to SoundWire core.
This commit is contained in:
Mark Brown
commit
1a75f24a7f
8
.mailmap
8
.mailmap
|
|
@ -416,6 +416,7 @@ Juha Yrjola <at solidboot.com>
|
|||
Juha Yrjola <juha.yrjola@nokia.com>
|
||||
Juha Yrjola <juha.yrjola@solidboot.com>
|
||||
Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
|
||||
Justin Iurman <justin.iurman@gmail.com> <justin.iurman@uliege.be>
|
||||
Iskren Chernev <me@iskren.info> <iskren.chernev@gmail.com>
|
||||
Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>
|
||||
Kalle Valo <kvalo@kernel.org> <quic_kvalo@quicinc.com>
|
||||
|
|
@ -472,6 +473,10 @@ Linas Vepstas <linas@austin.ibm.com>
|
|||
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
|
||||
Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
|
||||
Linus Lüssing <linus.luessing@c0d3.blue> <ll@simonwunderlich.de>
|
||||
Linus Walleij <linusw@kernel.org> <linus.walleij@ericsson.com>
|
||||
Linus Walleij <linusw@kernel.org> <linus.walleij@stericsson.com>
|
||||
Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
|
||||
Linus Walleij <linusw@kernel.org> <triad@df.lth.se>
|
||||
<linux-hardening@vger.kernel.org> <kernel-hardening@lists.openwall.com>
|
||||
Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
|
||||
Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
|
||||
|
|
@ -705,6 +710,8 @@ Sankeerth Billakanti <quic_sbillaka@quicinc.com> <sbillaka@codeaurora.org>
|
|||
Santosh Shilimkar <santosh.shilimkar@oracle.org>
|
||||
Santosh Shilimkar <ssantosh@kernel.org>
|
||||
Sarangdhar Joshi <spjoshi@codeaurora.org>
|
||||
Saravana Kannan <saravanak@kernel.org> <skannan@codeaurora.org>
|
||||
Saravana Kannan <saravanak@kernel.org> <saravanak@google.com>
|
||||
Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org>
|
||||
Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org>
|
||||
|
|
@ -794,6 +801,7 @@ Tanzir Hasan <tanzhasanwork@gmail.com> <tanzirh@google.com>
|
|||
Tejun Heo <htejun@gmail.com>
|
||||
Tomeu Vizoso <tomeu@tomeuvizoso.net> <tomeu.vizoso@collabora.com>
|
||||
Thomas Graf <tgraf@suug.ch>
|
||||
Thomas Gleixner <tglx@kernel.org> <tglx@linutronix.de>
|
||||
Thomas Körper <socketcan@esd.eu> <thomas.koerper@esd.eu>
|
||||
Thomas Pedersen <twp@codeaurora.org>
|
||||
Thorsten Blum <thorsten.blum@linux.dev> <thorsten.blum@toblux.com>
|
||||
|
|
|
|||
2
CREDITS
2
CREDITS
|
|
@ -1398,7 +1398,7 @@ D: SRM environment driver (for Alpha systems)
|
|||
P: 1024D/8399E1BB 250D 3BCF 7127 0D8C A444 A961 1DBD 5E75 8399 E1BB
|
||||
|
||||
N: Thomas Gleixner
|
||||
E: tglx@linutronix.de
|
||||
E: tglx@kernel.org
|
||||
D: NAND flash hardware support, JFFS2 on NAND flash
|
||||
|
||||
N: Jérôme Glisse
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
What: /sys/kernel/time/aux_clocks/<ID>/enable
|
||||
Date: May 2025
|
||||
Contact: Thomas Gleixner <tglx@linutronix.de>
|
||||
Contact: Thomas Gleixner <tglx@kernel.org>
|
||||
Description:
|
||||
Controls the enablement of auxiliary clock timekeepers.
|
||||
|
|
|
|||
|
|
@ -17,14 +17,14 @@ Date: January 2012
|
|||
contact: Lee Jones <lee@kernel.org>
|
||||
Description:
|
||||
Read-only attribute common to all SoCs. Contains the SoC machine
|
||||
name (e.g. Ux500).
|
||||
name (e.g. DB8500).
|
||||
|
||||
What: /sys/devices/socX/family
|
||||
Date: January 2012
|
||||
contact: Lee Jones <lee@kernel.org>
|
||||
Description:
|
||||
Read-only attribute common to all SoCs. Contains SoC family name
|
||||
(e.g. DB8500).
|
||||
(e.g. ux500).
|
||||
|
||||
On many of ARM based silicon with SMCCC v1.2+ compliant firmware
|
||||
this will contain the JEDEC JEP106 manufacturer’s identification
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ with the generic one and look at this one in parallel for the x86 specifics.
|
|||
Needless to say, code should use the generic functions - this file is *only*
|
||||
here to *document* the inner workings of x86 topology.
|
||||
|
||||
Started by Thomas Gleixner <tglx@linutronix.de> and Borislav Petkov <bp@alien8.de>.
|
||||
Started by Thomas Gleixner <tglx@kernel.org> and Borislav Petkov <bp@alien8.de>.
|
||||
|
||||
The main aim of the topology facilities is to present adequate interfaces to
|
||||
code which needs to know/query/use the structure of the running system wrt
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ CPU hotplug in the Kernel
|
|||
Srivatsa Vaddagiri <vatsa@in.ibm.com>,
|
||||
Ashok Raj <ashok.raj@intel.com>,
|
||||
Joel Schopp <jschopp@austin.ibm.com>,
|
||||
Thomas Gleixner <tglx@linutronix.de>
|
||||
Thomas Gleixner <tglx@kernel.org>
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
|
|
|||
|
|
@ -439,6 +439,6 @@ Credits
|
|||
|
||||
The following people have contributed to this document:
|
||||
|
||||
1. Thomas Gleixner tglx@linutronix.de
|
||||
1. Thomas Gleixner tglx@kernel.org
|
||||
|
||||
2. Ingo Molnar mingo@elte.hu
|
||||
|
|
|
|||
|
|
@ -209,4 +209,4 @@ testing. Thanks a lot.
|
|||
|
||||
The following people have contributed to this document:
|
||||
|
||||
Thomas Gleixner\ tglx@linutronix.de
|
||||
Thomas Gleixner\ tglx@kernel.org
|
||||
|
|
|
|||
|
|
@ -1105,7 +1105,6 @@ properties:
|
|||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
|
||||
- gocontroll,moduline-display # GOcontroll Moduline Display controller
|
||||
- prt,prt8ml # Protonic PRT8ML
|
||||
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
|
|
@ -1164,6 +1163,14 @@ properties:
|
|||
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Ka-Ro TX8P-ML81 SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- gocontroll,moduline-display
|
||||
- gocontroll,moduline-display-106
|
||||
- const: karo,tx8p-ml81
|
||||
- const: fsl,imx8mp
|
||||
|
||||
- description: Kontron i.MX8MP OSM-S SoM based Boards
|
||||
items:
|
||||
- const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board
|
||||
|
|
|
|||
|
|
@ -25,6 +25,10 @@ properties:
|
|||
items:
|
||||
- const: pci1de4,1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: The PCI Bus-Device-Function address.
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description: |
|
||||
|
|
@ -101,6 +105,7 @@ unevaluatedProperties: false
|
|||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#interrupt-cells'
|
||||
- interrupt-controller
|
||||
- pci-ep-bus@1
|
||||
|
|
@ -111,8 +116,9 @@ examples:
|
|||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rp1@0,0 {
|
||||
dev@0,0 {
|
||||
compatible = "pci1de4,1";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ title: Marvell MMP Timer
|
|||
|
||||
maintainers:
|
||||
- Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
- Thomas Gleixner <tglx@linutronix.de>
|
||||
- Thomas Gleixner <tglx@kernel.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -996,11 +996,11 @@ The following people have contributed to the NAND driver:
|
|||
|
||||
2. David Woodhouse\ dwmw2@infradead.org
|
||||
|
||||
3. Thomas Gleixner\ tglx@linutronix.de
|
||||
3. Thomas Gleixner\ tglx@kernel.org
|
||||
|
||||
A lot of users have provided bugfixes, improvements and helping hands
|
||||
for testing. Thanks a lot.
|
||||
|
||||
The following people have contributed to this document:
|
||||
|
||||
1. Thomas Gleixner\ tglx@linutronix.de
|
||||
1. Thomas Gleixner\ tglx@kernel.org
|
||||
|
|
|
|||
|
|
@ -416,6 +416,7 @@ lm_change yes no no
|
|||
lm_breaker_owns_lease: yes no no
|
||||
lm_lock_expirable yes no no
|
||||
lm_expire_lock no no yes
|
||||
lm_open_conflict yes no no
|
||||
====================== ============= ================= =========
|
||||
|
||||
buffer_head
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ attribute-sets:
|
|||
name: ifindex
|
||||
doc: |
|
||||
ifindex of the netdev to which the pool belongs.
|
||||
May be reported as 0 if the page pool was allocated for a netdev
|
||||
May not be reported if the page pool was allocated for a netdev
|
||||
which got destroyed already (page pools may outlast their netdevs
|
||||
because they wait for all memory to be returned).
|
||||
type: u32
|
||||
|
|
@ -601,7 +601,9 @@ operations:
|
|||
name: page-pool-get
|
||||
doc: |
|
||||
Get / dump information about Page Pools.
|
||||
(Only Page Pools associated with a net_device can be listed.)
|
||||
Only Page Pools associated by the driver with a net_device
|
||||
can be listed. ifindex will not be reported if the net_device
|
||||
no longer exists.
|
||||
attribute-set: page-pool
|
||||
do:
|
||||
request:
|
||||
|
|
|
|||
|
|
@ -57,8 +57,10 @@ Submitting Patches for Given SoC
|
|||
|
||||
All typical platform related patches should be sent via SoC submaintainers
|
||||
(platform-specific maintainers). This includes also changes to per-platform or
|
||||
shared defconfigs (scripts/get_maintainer.pl might not provide correct
|
||||
addresses in such case).
|
||||
shared defconfigs. Note that scripts/get_maintainer.pl might not provide
|
||||
correct addresses for the shared defconfig, so ignore its output and manually
|
||||
create CC-list based on MAINTAINERS file or use something like
|
||||
``scripts/get_maintainer.pl -f drivers/soc/FOO/``).
|
||||
|
||||
Submitting Patches to the Main SoC Maintainers
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -114,9 +116,9 @@ coordinating how the changes get merged through different maintainer trees.
|
|||
Usually the branch that includes a driver change will also include the
|
||||
corresponding change to the devicetree binding description, to ensure they are
|
||||
in fact compatible. This means that the devicetree branch can end up causing
|
||||
warnings in the "make dtbs_check" step. If a devicetree change depends on
|
||||
warnings in the ``make dtbs_check`` step. If a devicetree change depends on
|
||||
missing additions to a header file in include/dt-bindings/, it will fail the
|
||||
"make dtbs" step and not get merged.
|
||||
``make dtbs`` step and not get merged.
|
||||
|
||||
There are multiple ways to deal with this:
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
Srivatsa Vaddagiri <vatsa@in.ibm.com>,
|
||||
Ashok Raj <ashok.raj@intel.com>,
|
||||
Joel Schopp <jschopp@austin.ibm.com>,
|
||||
Thomas Gleixner <tglx@linutronix.de>
|
||||
Thomas Gleixner <tglx@kernel.org>
|
||||
|
||||
简介
|
||||
====
|
||||
|
|
|
|||
|
|
@ -404,6 +404,6 @@ kernel/irq/chip.c
|
|||
|
||||
感谢以下人士对本文档作出的贡献：
|
||||
|
||||
1. Thomas Gleixner tglx@linutronix.de
|
||||
1. Thomas Gleixner tglx@kernel.org
|
||||
|
||||
2. Ingo Molnar mingo@elte.hu
|
||||
|
|
|
|||
61
MAINTAINERS
61
MAINTAINERS
|
|
@ -1283,6 +1283,7 @@ F: include/uapi/drm/amdxdna_accel.h
|
|||
|
||||
AMD XGBE DRIVER
|
||||
M: "Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
|
||||
M: Raju Rangoju <Raju.Rangoju@amd.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
|
||||
|
|
@ -2011,7 +2012,7 @@ ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
|
|||
M: Arnd Bergmann <arnd@arndb.de>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
M: Linus Walleij <linus.walleij@linaro.org>
|
||||
M: Linus Walleij <linusw@kernel.org>
|
||||
R: Drew Fustini <fustini@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: soc@lists.linux.dev
|
||||
|
|
@ -2158,7 +2159,7 @@ M: Alice Ryhl <aliceryhl@google.com>
|
|||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
W: https://rust-for-linux.com/tyr-gpu-driver
|
||||
W https://drm.pages.freedesktop.org/maintainer-tools/drm-rust.html
|
||||
W: https://drm.pages.freedesktop.org/maintainer-tools/drm-rust.html
|
||||
B: https://gitlab.freedesktop.org/panfrost/linux/-/issues
|
||||
T: git https://gitlab.freedesktop.org/drm/rust/kernel.git
|
||||
F: Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
|
||||
|
|
@ -5801,7 +5802,8 @@ F: drivers/power/supply/cw2015_battery.c
|
|||
|
||||
CEPH COMMON CODE (LIBCEPH)
|
||||
M: Ilya Dryomov <idryomov@gmail.com>
|
||||
M: Xiubo Li <xiubli@redhat.com>
|
||||
M: Alex Markuze <amarkuze@redhat.com>
|
||||
M: Viacheslav Dubeyko <slava@dubeyko.com>
|
||||
L: ceph-devel@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://ceph.com/
|
||||
|
|
@ -5812,8 +5814,9 @@ F: include/linux/crush/
|
|||
F: net/ceph/
|
||||
|
||||
CEPH DISTRIBUTED FILE SYSTEM CLIENT (CEPH)
|
||||
M: Xiubo Li <xiubli@redhat.com>
|
||||
M: Ilya Dryomov <idryomov@gmail.com>
|
||||
M: Alex Markuze <amarkuze@redhat.com>
|
||||
M: Viacheslav Dubeyko <slava@dubeyko.com>
|
||||
L: ceph-devel@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://ceph.com/
|
||||
|
|
@ -6172,7 +6175,7 @@ F: include/linux/clk.h
|
|||
|
||||
CLOCKSOURCE, CLOCKEVENT DRIVERS
|
||||
M: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
|
||||
|
|
@ -6532,13 +6535,13 @@ F: rust/kernel/cpufreq.rs
|
|||
F: tools/testing/selftests/cpufreq/
|
||||
|
||||
CPU FREQUENCY DRIVERS - VIRTUAL MACHINE CPUFREQ
|
||||
M: Saravana Kannan <saravanak@google.com>
|
||||
M: Saravana Kannan <saravanak@kernel.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/cpufreq/virtual-cpufreq.c
|
||||
|
||||
CPU HOTPLUG
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Peter Zijlstra <peterz@infradead.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -6705,6 +6708,7 @@ S: Maintained
|
|||
T: git https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git libcrypto-next
|
||||
T: git https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git libcrypto-fixes
|
||||
F: lib/crypto/
|
||||
F: scripts/crypto/
|
||||
|
||||
CRYPTO SPEED TEST COMPARE
|
||||
M: Wang Jinchao <wangjinchao@xfusion.com>
|
||||
|
|
@ -6965,7 +6969,7 @@ F: Documentation/scsi/dc395x.rst
|
|||
F: drivers/scsi/dc395x.*
|
||||
|
||||
DEBUGOBJECTS:
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git core/debugobjects
|
||||
|
|
@ -7170,7 +7174,7 @@ F: drivers/base/devcoredump.c
|
|||
F: include/linux/devcoredump.h
|
||||
|
||||
DEVICE DEPENDENCY HELPER SCRIPT
|
||||
M: Saravana Kannan <saravanak@google.com>
|
||||
M: Saravana Kannan <saravanak@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: scripts/dev-needs.sh
|
||||
|
|
@ -8067,7 +8071,7 @@ W: https://rust-for-linux.com/nova-gpu-driver
|
|||
Q: https://patchwork.freedesktop.org/project/nouveau/
|
||||
B: https://gitlab.freedesktop.org/drm/nova/-/issues
|
||||
C: irc://irc.oftc.net/nouveau
|
||||
T: git https://gitlab.freedesktop.org/drm/nova.git nova-next
|
||||
T: git https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust-next
|
||||
F: Documentation/gpu/nova/
|
||||
F: drivers/gpu/nova-core/
|
||||
|
||||
|
|
@ -8079,7 +8083,7 @@ W: https://rust-for-linux.com/nova-gpu-driver
|
|||
Q: https://patchwork.freedesktop.org/project/nouveau/
|
||||
B: https://gitlab.freedesktop.org/drm/nova/-/issues
|
||||
C: irc://irc.oftc.net/nouveau
|
||||
T: git https://gitlab.freedesktop.org/drm/nova.git nova-next
|
||||
T: git https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust-next
|
||||
F: Documentation/gpu/nova/
|
||||
F: drivers/gpu/drm/nova/
|
||||
F: include/uapi/drm/nova_drm.h
|
||||
|
|
@ -8357,6 +8361,7 @@ X: drivers/gpu/drm/msm/
|
|||
X: drivers/gpu/drm/nova/
|
||||
X: drivers/gpu/drm/radeon/
|
||||
X: drivers/gpu/drm/tegra/
|
||||
X: drivers/gpu/drm/tyr/
|
||||
X: drivers/gpu/drm/xe/
|
||||
|
||||
DRM DRIVERS AND COMMON INFRASTRUCTURE [RUST]
|
||||
|
|
@ -10367,7 +10372,7 @@ F: include/uapi/linux/fuse.h
|
|||
F: tools/testing/selftests/filesystems/fuse/
|
||||
|
||||
FUTEX SUBSYSTEM
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Ingo Molnar <mingo@redhat.com>
|
||||
R: Peter Zijlstra <peterz@infradead.org>
|
||||
R: Darren Hart <dvhart@infradead.org>
|
||||
|
|
@ -10511,7 +10516,7 @@ F: drivers/base/arch_topology.c
|
|||
F: include/linux/arch_topology.h
|
||||
|
||||
GENERIC ENTRY CODE
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Peter Zijlstra <peterz@infradead.org>
|
||||
M: Andy Lutomirski <luto@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
|
|
@ -10624,7 +10629,7 @@ F: drivers/uio/uio_pci_generic.c
|
|||
|
||||
GENERIC VDSO LIBRARY
|
||||
M: Andy Lutomirski <luto@kernel.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Vincenzo Frascino <vincenzo.frascino@arm.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -11237,7 +11242,7 @@ F: drivers/hid/hid-logitech-hidpp.c
|
|||
HIGH-RESOLUTION TIMERS, TIMER WHEEL, CLOCKEVENTS
|
||||
M: Anna-Maria Behnsen <anna-maria@linutronix.de>
|
||||
M: Frederic Weisbecker <frederic@kernel.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
|
||||
|
|
@ -11260,7 +11265,7 @@ R: Boqun Feng <boqun.feng@gmail.com>
|
|||
R: FUJITA Tomonori <fujita.tomonori@gmail.com>
|
||||
R: Frederic Weisbecker <frederic@kernel.org>
|
||||
R: Lyude Paul <lyude@redhat.com>
|
||||
R: Thomas Gleixner <tglx@linutronix.de>
|
||||
R: Thomas Gleixner <tglx@kernel.org>
|
||||
R: Anna-Maria Behnsen <anna-maria@linutronix.de>
|
||||
R: John Stultz <jstultz@google.com>
|
||||
R: Stephen Boyd <sboyd@kernel.org>
|
||||
|
|
@ -13330,7 +13335,7 @@ F: Documentation/devicetree/bindings/sound/irondevice,*
|
|||
F: sound/soc/codecs/sma*
|
||||
|
||||
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
|
||||
F: Documentation/core-api/irq/irq-domain.rst
|
||||
|
|
@ -13340,7 +13345,7 @@ F: kernel/irq/irqdomain.c
|
|||
F: kernel/irq/msi.c
|
||||
|
||||
IRQ SUBSYSTEM
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
|
||||
|
|
@ -13353,7 +13358,7 @@ F: kernel/irq/
|
|||
F: lib/group_cpus.c
|
||||
|
||||
IRQCHIP DRIVERS
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
|
||||
|
|
@ -14447,7 +14452,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm.git mm-nonmm-unstab
|
|||
F: lib/*
|
||||
|
||||
LICENSES and SPDX stuff
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
L: linux-spdx@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -18283,7 +18288,7 @@ X: net/wireless/
|
|||
X: tools/testing/selftests/net/can/
|
||||
|
||||
NETWORKING [IOAM]
|
||||
M: Justin Iurman <justin.iurman@uliege.be>
|
||||
M: Justin Iurman <justin.iurman@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/networking/ioam6*
|
||||
F: include/linux/ioam6*
|
||||
|
|
@ -18572,7 +18577,7 @@ NOHZ, DYNTICKS SUPPORT
|
|||
M: Anna-Maria Behnsen <anna-maria@linutronix.de>
|
||||
M: Frederic Weisbecker <frederic@kernel.org>
|
||||
M: Ingo Molnar <mingo@kernel.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/nohz
|
||||
|
|
@ -19547,7 +19552,7 @@ F: include/linux/oa_tc6.h
|
|||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
M: Saravana Kannan <saravanak@google.com>
|
||||
M: Saravana Kannan <saravanak@kernel.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
S: Maintained
|
||||
Q: http://patchwork.kernel.org/project/devicetree/list/
|
||||
|
|
@ -20757,7 +20762,7 @@ F: drivers/platform/x86/portwell-ec.c
|
|||
POSIX CLOCKS and TIMERS
|
||||
M: Anna-Maria Behnsen <anna-maria@linutronix.de>
|
||||
M: Frederic Weisbecker <frederic@kernel.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
|
||||
|
|
@ -26268,7 +26273,7 @@ F: drivers/net/wireless/ti/
|
|||
|
||||
TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
|
||||
M: John Stultz <jstultz@google.com>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
R: Stephen Boyd <sboyd@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
|
|
@ -28199,7 +28204,7 @@ F: net/lapb/
|
|||
F: net/x25/
|
||||
|
||||
X86 ARCHITECTURE (32-BIT AND 64-BIT)
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Ingo Molnar <mingo@redhat.com>
|
||||
M: Borislav Petkov <bp@alien8.de>
|
||||
M: Dave Hansen <dave.hansen@linux.intel.com>
|
||||
|
|
@ -28215,7 +28220,7 @@ F: tools/testing/selftests/x86
|
|||
|
||||
X86 CPUID DATABASE
|
||||
M: Borislav Petkov <bp@alien8.de>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: x86@kernel.org
|
||||
R: Ahmed S. Darwish <darwi@linutronix.de>
|
||||
L: x86-cpuid@lists.linux.dev
|
||||
|
|
@ -28231,7 +28236,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
|
|||
F: arch/x86/entry/
|
||||
|
||||
X86 HARDWARE VULNERABILITIES
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
M: Thomas Gleixner <tglx@kernel.org>
|
||||
M: Borislav Petkov <bp@alien8.de>
|
||||
M: Peter Zijlstra <peterz@infradead.org>
|
||||
M: Josh Poimboeuf <jpoimboe@kernel.org>
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -2,7 +2,7 @@
|
|||
VERSION = 6
|
||||
PATCHLEVEL = 19
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Baby Opossum Posse
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -12,6 +12,17 @@ / {
|
|||
model = "Actiontec MI424WR rev A/C";
|
||||
compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
|
||||
|
||||
/* Connect the switch to EthC */
|
||||
spi {
|
||||
ethernet-switch@0 {
|
||||
ethernet-ports {
|
||||
ethernet-port@4 {
|
||||
ethernet = <ðc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/* EthB used for WAN */
|
||||
ethernet@c8009000 {
|
||||
|
|
|
|||
|
|
@ -12,6 +12,17 @@ / {
|
|||
model = "Actiontec MI424WR rev D";
|
||||
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
|
||||
|
||||
/* Connect the switch to EthB */
|
||||
spi {
|
||||
ethernet-switch@0 {
|
||||
ethernet-ports {
|
||||
ethernet-port@4 {
|
||||
ethernet = <ðb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/* EthB used for LAN */
|
||||
ethernet@c8009000 {
|
||||
|
|
|
|||
|
|
@ -152,7 +152,6 @@ ethernet-port@3 {
|
|||
};
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
ethernet = <ðc>;
|
||||
phy-mode = "mii";
|
||||
fixed-link {
|
||||
speed = <100>;
|
||||
|
|
|
|||
|
|
@ -248,14 +248,14 @@ ledr3: led@9 {
|
|||
linux,default-trigger = "nand-disk";
|
||||
};
|
||||
|
||||
ledg3: led@10 {
|
||||
reg = <10>;
|
||||
ledg3: led@a {
|
||||
reg = <0xa>;
|
||||
label = "system:green3:live";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
ledb3: led@11 {
|
||||
reg = <11>;
|
||||
ledb3: led@b {
|
||||
reg = <0xb>;
|
||||
label = "system:blue3:cpu";
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -398,13 +398,13 @@ leds {
|
|||
#size-cells = <0>;
|
||||
led-control = <0x0 0x0 0x3f83f8 0x0>;
|
||||
|
||||
sysled0@3 {
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
label = "system:green:status";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
sysled1@4 {
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
label = "system:green:act";
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
|
|||
|
|
@ -225,13 +225,13 @@ leds {
|
|||
#size-cells = <0>;
|
||||
led-control = <0x0 0x0 0x3f83f8 0x0>;
|
||||
|
||||
sysled3: led3@3 {
|
||||
sysled3: led@3 {
|
||||
reg = <3>;
|
||||
label = "system:red:power";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
sysled4: led4@4 {
|
||||
sysled4: led@4 {
|
||||
reg = <4>;
|
||||
label = "system:green:act";
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
|
|||
|
|
@ -153,13 +153,13 @@ leds {
|
|||
#size-cells = <0>;
|
||||
led-control = <0x0 0x0 0x3f83f8 0x0>;
|
||||
|
||||
sysled3: led3@3 {
|
||||
sysled3: led@3 {
|
||||
reg = <3>;
|
||||
label = "system:red:power";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
sysled4: led4@4 {
|
||||
sysled4: led@4 {
|
||||
reg = <4>;
|
||||
label = "system:green:act";
|
||||
linux,default-trigger = "heartbeat";
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ rtc@32 {
|
|||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
reg = <0x32>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,15 +7,13 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
|
|||
bcm2711-rpi-4-b.dtb \
|
||||
bcm2711-rpi-cm4-io.dtb \
|
||||
bcm2712-rpi-5-b.dtb \
|
||||
bcm2712-rpi-5-b-ovl-rp1.dtb \
|
||||
bcm2712-d-rpi-5-b.dtb \
|
||||
bcm2837-rpi-2-b.dtb \
|
||||
bcm2837-rpi-3-a-plus.dtb \
|
||||
bcm2837-rpi-3-b.dtb \
|
||||
bcm2837-rpi-3-b-plus.dtb \
|
||||
bcm2837-rpi-cm3-io3.dtb \
|
||||
bcm2837-rpi-zero-2-w.dtb \
|
||||
rp1.dtbo
|
||||
bcm2837-rpi-zero-2-w.dtb
|
||||
|
||||
subdir-y += bcmbca
|
||||
subdir-y += northstar2
|
||||
|
|
|
|||
|
|
@ -1,22 +1,16 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
|
||||
* the RP1 driver to load the RP1 dtb overlay at runtime, while
|
||||
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
|
||||
* already contains RP1 node, so no overlay is loaded nor needed).
|
||||
* This file is intended to host the override nodes for the RP1 peripherals,
|
||||
* e.g. to declare the phy of the ethernet interface or the custom pin setup
|
||||
* for several RP1 peripherals.
|
||||
* This in turn is due to the fact that there's no current generic
|
||||
* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
|
||||
* are not yet defined in the DT since they are loaded at runtime via overlay.
|
||||
* As a loose attempt to separate RP1 customizations from SoC peripherals
|
||||
* definitioni, this file is intended to host the override nodes for the RP1
|
||||
* peripherals, e.g. to declare the phy of the ethernet interface or custom
|
||||
* pin setup.
|
||||
* All other nodes that do not have anything to do with RP1 should be added
|
||||
* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
|
||||
* to the included bcm2712-rpi-5-b-base.dtsi instead.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
|
||||
#include "bcm2712-rpi-5-b-base.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -25,7 +19,26 @@ aliases {
|
|||
};
|
||||
|
||||
&pcie2 {
|
||||
#include "rp1-nexus.dtsi"
|
||||
pci@0,0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
ranges;
|
||||
bus-range = <0 1>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dev@0,0 {
|
||||
compatible = "pci1de4,1";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
#include "rp1-common.dtsi"
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rp1_eth {
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
|
||||
rp1_nexus {
|
||||
compatible = "pci1de4,1";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01 0x00 0x00000000
|
||||
0x02000000 0x00 0x00000000
|
||||
0x0 0x400000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
#include "rp1-common.dtsi"
|
||||
};
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&pcie2 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
#include "rp1-nexus.dtsi"
|
||||
};
|
||||
|
|
@ -113,6 +113,7 @@ mdio {
|
|||
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
|
||||
compatible = "ethernet-phy-id0007.c110",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
clocks = <&clk IMX8MP_CLK_ENET_QOS>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&pinctrl_ethphy0>;
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#include "imx8mp-tx8p-ml81.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "gocontroll,moduline-display", "fsl,imx8mp";
|
||||
compatible = "gocontroll,moduline-display-106", "karo,tx8p-ml81", "fsl,imx8mp";
|
||||
chassis-type = "embedded";
|
||||
hardware = "Moduline Display V1.06";
|
||||
model = "GOcontroll Moduline Display baseboard";
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ &eqos {
|
|||
<&clk IMX8MP_SYS_PLL2_100M>,
|
||||
<&clk IMX8MP_SYS_PLL2_50M>;
|
||||
assigned-clock-rates = <266000000>, <100000000>, <50000000>;
|
||||
nvmem-cells = <ð_mac1>;
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rmii";
|
||||
pinctrl-0 = <&pinctrl_eqos>;
|
||||
|
|
@ -75,6 +76,10 @@ ethphy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
nvmem-cells = <ð_mac2>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "SODIMM_152",
|
||||
"SODIMM_42",
|
||||
|
|
|
|||
|
|
@ -263,6 +263,7 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
|
|||
regulator-max-microvolt = <3000000>;
|
||||
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
off-on-delay-us = <4800>;
|
||||
};
|
||||
|
||||
reg_audio: regulator-audio {
|
||||
|
|
@ -576,7 +577,7 @@ light-sensor@44 {
|
|||
compatible = "isil,isl29023";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&lsio_gpio4>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
pressure-sensor@60 {
|
||||
|
|
|
|||
|
|
@ -172,25 +172,25 @@ &flexcan3 {
|
|||
|
||||
&lpuart0 {
|
||||
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
|
||||
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
|
||||
dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
|
||||
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
|
||||
dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
&lpuart2 {
|
||||
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
|
||||
dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
|
||||
dmas = <&edma2 16 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
&lpuart3 {
|
||||
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
|
||||
dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
|
||||
dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -406,8 +406,6 @@ som_gpio_expander_1: gpio@21 {
|
|||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"SMARC_SDIO_WP";
|
||||
};
|
||||
|
||||
|
|
@ -582,7 +580,7 @@ &netc_emdio {
|
|||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&som_gpio_expander_1>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -828,7 +828,7 @@ i3c2: i3c@42520000 {
|
|||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&scmi_clk IMX95_CLK_BUSAON>,
|
||||
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
|
||||
<&scmi_clk IMX95_CLK_I3C2SLOW>;
|
||||
clock-names = "pclk", "fast_clk";
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ ethphy0: ethernet-phy@e {
|
|||
reset-assert-us = <500000>;
|
||||
reset-deassert-us = <500>;
|
||||
interrupt-parent = <&expander2>;
|
||||
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -675,10 +675,7 @@ &dwc3 { /* USB */
|
|||
snps,lfps_filter_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,tx_de_emphasis_quirk;
|
||||
snps,tx_de_emphasis = <1>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,gctl-reset-quirk;
|
||||
usb-role-switch;
|
||||
role-switch-default-mode = "host";
|
||||
port {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ &mcasp1 {
|
|||
};
|
||||
|
||||
&main_pmx0 {
|
||||
gpmc0_pins_default: gpmc0-pins-default {
|
||||
gpmc0_pins_default: gpmc0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
|
||||
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
|
||||
|
|
|
|||
|
|
@ -30,13 +30,10 @@ icssg1-ethernet {
|
|||
<&main_pktdma 0xc206 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0xc207 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
|
||||
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
|
||||
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
|
||||
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
|
||||
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
|
||||
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
|
||||
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
|
||||
"rx0", "rx1",
|
||||
"rxmgm0", "rxmgm1";
|
||||
"rx0", "rx1";
|
||||
|
||||
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
|
||||
|
|
|
|||
|
|
@ -20,13 +20,13 @@ aliases {
|
|||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
|
||||
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi1_pins_default: main-spi1-pins-default {
|
||||
main_spi1_pins_default: main-spi1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
|
||||
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
|
||||
|
|
@ -35,7 +35,7 @@ AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */
|
|||
>;
|
||||
};
|
||||
|
||||
main_uart3_pins_default: main-uart3-pins-default {
|
||||
main_uart3_pins_default: main-uart3-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
|
||||
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
|
||||
|
|
@ -52,7 +52,7 @@ &main_gpio1 {
|
|||
&main_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi1_pins_default>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ void arch_efi_call_virt_teardown(void);
|
|||
* switching to the EFI runtime stack.
|
||||
*/
|
||||
#define current_in_efi() \
|
||||
(!preemptible() && efi_rt_stack_top != NULL && \
|
||||
(efi_rt_stack_top != NULL && \
|
||||
on_task_stack(current, READ_ONCE(efi_rt_stack_top[-1]), 1))
|
||||
|
||||
#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#ifndef __ASM_SUSPEND_H
|
||||
#define __ASM_SUSPEND_H
|
||||
|
||||
#define NR_CTX_REGS 13
|
||||
#define NR_CTX_REGS 14
|
||||
#define NR_CALLEE_SAVED_REGS 12
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -171,7 +171,8 @@ static int change_memory_common(unsigned long addr, int numpages,
|
|||
*/
|
||||
area = find_vm_area((void *)addr);
|
||||
if (!area ||
|
||||
end > (unsigned long)kasan_reset_tag(area->addr) + area->size ||
|
||||
((unsigned long)kasan_reset_tag((void *)end) >
|
||||
(unsigned long)kasan_reset_tag(area->addr) + area->size) ||
|
||||
((area->flags & (VM_ALLOC | VM_ALLOW_HUGE_VMAP)) != VM_ALLOC))
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -184,7 +185,8 @@ static int change_memory_common(unsigned long addr, int numpages,
|
|||
*/
|
||||
if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
|
||||
pgprot_val(clear_mask) == PTE_RDONLY)) {
|
||||
unsigned long idx = (start - (unsigned long)kasan_reset_tag(area->addr))
|
||||
unsigned long idx = ((unsigned long)kasan_reset_tag((void *)start) -
|
||||
(unsigned long)kasan_reset_tag(area->addr))
|
||||
>> PAGE_SHIFT;
|
||||
for (; numpages; idx++, numpages--) {
|
||||
ret = __change_memory_common((u64)page_address(area->pages[idx]),
|
||||
|
|
|
|||
|
|
@ -110,6 +110,10 @@ SYM_FUNC_START(cpu_do_suspend)
|
|||
* call stack.
|
||||
*/
|
||||
str x18, [x0, #96]
|
||||
alternative_if ARM64_HAS_TCR2
|
||||
mrs x2, REG_TCR2_EL1
|
||||
str x2, [x0, #104]
|
||||
alternative_else_nop_endif
|
||||
ret
|
||||
SYM_FUNC_END(cpu_do_suspend)
|
||||
|
||||
|
|
@ -144,6 +148,10 @@ SYM_FUNC_START(cpu_do_resume)
|
|||
msr tcr_el1, x8
|
||||
msr vbar_el1, x9
|
||||
msr mdscr_el1, x10
|
||||
alternative_if ARM64_HAS_TCR2
|
||||
ldr x2, [x0, #104]
|
||||
msr REG_TCR2_EL1, x2
|
||||
alternative_else_nop_endif
|
||||
|
||||
msr sctlr_el1, x12
|
||||
set_this_cpu_offset x13
|
||||
|
|
|
|||
|
|
@ -31,11 +31,7 @@ $(obj)/xipImage: vmlinux FORCE
|
|||
|
||||
endif
|
||||
|
||||
ifdef CONFIG_RELOCATABLE
|
||||
$(obj)/Image: vmlinux.unstripped FORCE
|
||||
else
|
||||
$(obj)/Image: vmlinux FORCE
|
||||
endif
|
||||
$(call if_changed,objcopy)
|
||||
|
||||
$(obj)/Image.gz: $(obj)/Image FORCE
|
||||
|
|
|
|||
|
|
@ -55,7 +55,6 @@ CONFIG_DEVTMPFS_MOUNT=y
|
|||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_DEVMEM is not set
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_I2C_COMPAT is not set
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_HELPER_AUTO is not set
|
||||
CONFIG_I2C_DESIGNWARE_CORE=y
|
||||
|
|
@ -89,7 +88,6 @@ CONFIG_PRINTK_TIME=y
|
|||
# CONFIG_FRAME_POINTER is not set
|
||||
# CONFIG_DEBUG_MISC is not set
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
|
|
|
|||
|
|
@ -86,7 +86,6 @@ CONFIG_PRINTK_TIME=y
|
|||
# CONFIG_FRAME_POINTER is not set
|
||||
# CONFIG_DEBUG_MISC is not set
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
|
|
|
|||
|
|
@ -66,7 +66,6 @@ CONFIG_EXT2_FS=y
|
|||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_LSM="[]"
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#endif /* _LINUX_BITOPS_H */
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/bitsperlong.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -124,10 +124,6 @@
|
|||
#ifdef CONFIG_64BIT
|
||||
#include <asm/pgtable-64.h>
|
||||
|
||||
#define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1))
|
||||
#define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1))
|
||||
#define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1))
|
||||
|
||||
#define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS)
|
||||
#define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39)
|
||||
#define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64)
|
||||
|
|
|
|||
|
|
@ -3,12 +3,6 @@
|
|||
# Makefile for the RISC-V Linux kernel
|
||||
#
|
||||
|
||||
ifdef CONFIG_FTRACE
|
||||
CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_patch.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_sbi.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_return_address.o = $(CC_FLAGS_FTRACE)
|
||||
endif
|
||||
CFLAGS_syscall_table.o += $(call cc-disable-warning, override-init)
|
||||
CFLAGS_compat_syscall_table.o += $(call cc-disable-warning, override-init)
|
||||
|
||||
|
|
@ -24,7 +18,6 @@ CFLAGS_sbi_ecall.o := -mcmodel=medany
|
|||
ifdef CONFIG_FTRACE
|
||||
CFLAGS_REMOVE_alternative.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_cpufeature.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_sbi_ecall.o = $(CC_FLAGS_FTRACE)
|
||||
endif
|
||||
ifdef CONFIG_RELOCATABLE
|
||||
CFLAGS_alternative.o += -fno-pie
|
||||
|
|
@ -43,6 +36,14 @@ CFLAGS_sbi_ecall.o += -D__NO_FORTIFY
|
|||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_FTRACE
|
||||
CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_patch.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_sbi.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_return_address.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_sbi_ecall.o = $(CC_FLAGS_FTRACE)
|
||||
endif
|
||||
|
||||
always-$(KBUILD_BUILTIN) += vmlinux.lds
|
||||
|
||||
obj-y += head.o
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ static void sbi_cpu_stop(void)
|
|||
int ret;
|
||||
|
||||
ret = sbi_hsm_hart_stop();
|
||||
pr_crit("Unable to stop the cpu %u (%d)\n", smp_processor_id(), ret);
|
||||
pr_crit("Unable to stop the cpu %d (%d)\n", smp_processor_id(), ret);
|
||||
}
|
||||
|
||||
static int sbi_cpu_is_stopped(unsigned int cpuid)
|
||||
|
|
|
|||
|
|
@ -301,23 +301,22 @@ static const unsigned int riscv_a_exts[] = {
|
|||
RISCV_ISA_EXT_ZALRSC,
|
||||
};
|
||||
|
||||
#define RISCV_ISA_EXT_ZKN \
|
||||
RISCV_ISA_EXT_ZBKB, \
|
||||
RISCV_ISA_EXT_ZBKC, \
|
||||
RISCV_ISA_EXT_ZBKX, \
|
||||
RISCV_ISA_EXT_ZKND, \
|
||||
RISCV_ISA_EXT_ZKNE, \
|
||||
RISCV_ISA_EXT_ZKNH
|
||||
|
||||
static const unsigned int riscv_zk_bundled_exts[] = {
|
||||
RISCV_ISA_EXT_ZBKB,
|
||||
RISCV_ISA_EXT_ZBKC,
|
||||
RISCV_ISA_EXT_ZBKX,
|
||||
RISCV_ISA_EXT_ZKND,
|
||||
RISCV_ISA_EXT_ZKNE,
|
||||
RISCV_ISA_EXT_ZKN,
|
||||
RISCV_ISA_EXT_ZKR,
|
||||
RISCV_ISA_EXT_ZKT,
|
||||
RISCV_ISA_EXT_ZKT
|
||||
};
|
||||
|
||||
static const unsigned int riscv_zkn_bundled_exts[] = {
|
||||
RISCV_ISA_EXT_ZBKB,
|
||||
RISCV_ISA_EXT_ZBKC,
|
||||
RISCV_ISA_EXT_ZBKX,
|
||||
RISCV_ISA_EXT_ZKND,
|
||||
RISCV_ISA_EXT_ZKNE,
|
||||
RISCV_ISA_EXT_ZKNH,
|
||||
RISCV_ISA_EXT_ZKN
|
||||
};
|
||||
|
||||
static const unsigned int riscv_zks_bundled_exts[] = {
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ static int image_probe(const char *kernel_buf, unsigned long kernel_len)
|
|||
if (!h || kernel_len < sizeof(*h))
|
||||
return -EINVAL;
|
||||
|
||||
/* According to Documentation/riscv/boot-image-header.rst,
|
||||
/* According to Documentation/arch/riscv/boot-image-header.rst,
|
||||
* use "magic2" field to check when version >= 0.2.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -181,6 +181,7 @@ SYM_FUNC_END(test_kprobes_c_bnez)
|
|||
|
||||
#endif /* CONFIG_RISCV_ISA_C */
|
||||
|
||||
.section .rodata
|
||||
SYM_DATA_START(test_kprobes_addresses)
|
||||
RISCV_PTR test_kprobes_add_addr1
|
||||
RISCV_PTR test_kprobes_add_addr2
|
||||
|
|
@ -212,6 +213,7 @@ SYM_DATA_START(test_kprobes_addresses)
|
|||
RISCV_PTR 0
|
||||
SYM_DATA_END(test_kprobes_addresses)
|
||||
|
||||
.section .rodata
|
||||
SYM_DATA_START(test_kprobes_functions)
|
||||
RISCV_PTR test_kprobes_add
|
||||
RISCV_PTR test_kprobes_jal
|
||||
|
|
|
|||
|
|
@ -339,8 +339,10 @@ void do_trap_ecall_u(struct pt_regs *regs)
|
|||
|
||||
add_random_kstack_offset();
|
||||
|
||||
if (syscall >= 0 && syscall < NR_syscalls)
|
||||
if (syscall >= 0 && syscall < NR_syscalls) {
|
||||
syscall = array_index_nospec(syscall, NR_syscalls);
|
||||
syscall_handler(regs, syscall);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ultimately, this value will get limited by KSTACK_OFFSET_MAX(),
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
* Heavily based on the x86 and PowerPC implementations.
|
||||
*
|
||||
* x86:
|
||||
* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
|
||||
* Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
|
||||
* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
|
||||
* Copyright (C) 2009 Jaswinder Singh Rajput
|
||||
* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
|
||||
|
|
|
|||
|
|
@ -181,6 +181,28 @@ static int __init ofpci_debug(char *str)
|
|||
|
||||
__setup("ofpci_debug=", ofpci_debug);
|
||||
|
||||
static void of_fixup_pci_pref(struct pci_dev *dev, int index,
|
||||
struct resource *res)
|
||||
{
|
||||
struct pci_bus_region region;
|
||||
|
||||
if (!(res->flags & IORESOURCE_MEM_64))
|
||||
return;
|
||||
|
||||
if (!resource_size(res))
|
||||
return;
|
||||
|
||||
pcibios_resource_to_bus(dev->bus, ®ion, res);
|
||||
if (region.end <= ~((u32)0))
|
||||
return;
|
||||
|
||||
if (!(res->flags & IORESOURCE_PREFETCH)) {
|
||||
res->flags |= IORESOURCE_PREFETCH;
|
||||
pci_info(dev, "reg 0x%x: fixup: pref added to 64-bit resource\n",
|
||||
index);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long pci_parse_of_flags(u32 addr0)
|
||||
{
|
||||
unsigned long flags = 0;
|
||||
|
|
@ -244,6 +266,7 @@ static void pci_parse_of_addrs(struct platform_device *op,
|
|||
res->end = op_res->end;
|
||||
res->flags = flags;
|
||||
res->name = pci_name(dev);
|
||||
of_fixup_pci_pref(dev, i, res);
|
||||
|
||||
pci_info(dev, "reg 0x%x: %pR\n", i, res);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
* This code is based almost entirely upon the x86 perf event
|
||||
* code, which is:
|
||||
*
|
||||
* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
|
||||
* Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
|
||||
* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
|
||||
* Copyright (C) 2009 Jaswinder Singh Rajput
|
||||
* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
|
||||
|
|
|
|||
|
|
@ -8,3 +8,5 @@ UBSAN_SANITIZE_noinstr.o := n
|
|||
# GCC may fail to respect __no_sanitize_address or __no_kcsan when inlining
|
||||
KASAN_SANITIZE_noinstr.o := n
|
||||
KCSAN_SANITIZE_noinstr.o := n
|
||||
|
||||
GCOV_PROFILE_noinstr.o := n
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Performance events x86 architecture code
|
||||
*
|
||||
* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
|
||||
* Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
|
||||
* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
|
||||
* Copyright (C) 2009 Jaswinder Singh Rajput
|
||||
* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Performance events x86 architecture header
|
||||
*
|
||||
* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
|
||||
* Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
|
||||
* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
|
||||
* Copyright (C) 2009 Jaswinder Singh Rajput
|
||||
* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
|
||||
* Copyright (C) 2009 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
|
||||
*
|
||||
* For licencing details see kernel-base/COPYING
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
* Signed-off-by: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
|
||||
*
|
||||
* Major changes to the original code by: Dave Hansen <dave.hansen@intel.com>
|
||||
* Mostly rewritten by Thomas Gleixner <tglx@linutronix.de> and
|
||||
* Mostly rewritten by Thomas Gleixner <tglx@kernel.org> and
|
||||
* Andy Lutomirsky <luto@amacapital.net>
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
|
|
|||
|
|
@ -140,14 +140,21 @@ EXPORT_SYMBOL_GPL(blk_rq_integrity_map_user);
|
|||
bool blk_integrity_merge_rq(struct request_queue *q, struct request *req,
|
||||
struct request *next)
|
||||
{
|
||||
struct bio_integrity_payload *bip, *bip_next;
|
||||
|
||||
if (blk_integrity_rq(req) == 0 && blk_integrity_rq(next) == 0)
|
||||
return true;
|
||||
|
||||
if (blk_integrity_rq(req) == 0 || blk_integrity_rq(next) == 0)
|
||||
return false;
|
||||
|
||||
if (bio_integrity(req->bio)->bip_flags !=
|
||||
bio_integrity(next->bio)->bip_flags)
|
||||
bip = bio_integrity(req->bio);
|
||||
bip_next = bio_integrity(next->bio);
|
||||
if (bip->bip_flags != bip_next->bip_flags)
|
||||
return false;
|
||||
|
||||
if (bip->bip_flags & BIP_CHECK_APPTAG &&
|
||||
bip->app_tag != bip_next->app_tag)
|
||||
return false;
|
||||
|
||||
if (req->nr_integrity_segments + next->nr_integrity_segments >
|
||||
|
|
@ -163,15 +170,21 @@ bool blk_integrity_merge_rq(struct request_queue *q, struct request *req,
|
|||
bool blk_integrity_merge_bio(struct request_queue *q, struct request *req,
|
||||
struct bio *bio)
|
||||
{
|
||||
struct bio_integrity_payload *bip, *bip_bio = bio_integrity(bio);
|
||||
int nr_integrity_segs;
|
||||
|
||||
if (blk_integrity_rq(req) == 0 && bio_integrity(bio) == NULL)
|
||||
if (blk_integrity_rq(req) == 0 && bip_bio == NULL)
|
||||
return true;
|
||||
|
||||
if (blk_integrity_rq(req) == 0 || bio_integrity(bio) == NULL)
|
||||
if (blk_integrity_rq(req) == 0 || bip_bio == NULL)
|
||||
return false;
|
||||
|
||||
if (bio_integrity(req->bio)->bip_flags != bio_integrity(bio)->bip_flags)
|
||||
bip = bio_integrity(req->bio);
|
||||
if (bip->bip_flags != bip_bio->bip_flags)
|
||||
return false;
|
||||
|
||||
if (bip->bip_flags & BIP_CHECK_APPTAG &&
|
||||
bip->app_tag != bip_bio->app_tag)
|
||||
return false;
|
||||
|
||||
nr_integrity_segs = blk_rq_count_integrity_sg(q, bio);
|
||||
|
|
|
|||
|
|
@ -4553,8 +4553,7 @@ static void __blk_mq_realloc_hw_ctxs(struct blk_mq_tag_set *set,
|
|||
* Make sure reading the old queue_hw_ctx from other
|
||||
* context concurrently won't trigger uaf.
|
||||
*/
|
||||
synchronize_rcu_expedited();
|
||||
kfree(hctxs);
|
||||
kfree_rcu_mightsleep(hctxs);
|
||||
hctxs = new_hctxs;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -112,29 +112,26 @@ void __rq_qos_queue_depth_changed(struct rq_qos *rqos);
|
|||
|
||||
static inline void rq_qos_cleanup(struct request_queue *q, struct bio *bio)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos)
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos)
|
||||
__rq_qos_cleanup(q->rq_qos, bio);
|
||||
}
|
||||
|
||||
static inline void rq_qos_done(struct request_queue *q, struct request *rq)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos && !blk_rq_is_passthrough(rq))
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) &&
|
||||
q->rq_qos && !blk_rq_is_passthrough(rq))
|
||||
__rq_qos_done(q->rq_qos, rq);
|
||||
}
|
||||
|
||||
static inline void rq_qos_issue(struct request_queue *q, struct request *rq)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos)
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos)
|
||||
__rq_qos_issue(q->rq_qos, rq);
|
||||
}
|
||||
|
||||
static inline void rq_qos_requeue(struct request_queue *q, struct request *rq)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos)
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos)
|
||||
__rq_qos_requeue(q->rq_qos, rq);
|
||||
}
|
||||
|
||||
|
|
@ -162,8 +159,7 @@ static inline void rq_qos_done_bio(struct bio *bio)
|
|||
|
||||
static inline void rq_qos_throttle(struct request_queue *q, struct bio *bio)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos) {
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos) {
|
||||
bio_set_flag(bio, BIO_QOS_THROTTLED);
|
||||
__rq_qos_throttle(q->rq_qos, bio);
|
||||
}
|
||||
|
|
@ -172,16 +168,14 @@ static inline void rq_qos_throttle(struct request_queue *q, struct bio *bio)
|
|||
static inline void rq_qos_track(struct request_queue *q, struct request *rq,
|
||||
struct bio *bio)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos)
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos)
|
||||
__rq_qos_track(q->rq_qos, rq, bio);
|
||||
}
|
||||
|
||||
static inline void rq_qos_merge(struct request_queue *q, struct request *rq,
|
||||
struct bio *bio)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos) {
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos) {
|
||||
bio_set_flag(bio, BIO_QOS_MERGED);
|
||||
__rq_qos_merge(q->rq_qos, rq, bio);
|
||||
}
|
||||
|
|
@ -189,8 +183,7 @@ static inline void rq_qos_merge(struct request_queue *q, struct request *rq,
|
|||
|
||||
static inline void rq_qos_queue_depth_changed(struct request_queue *q)
|
||||
{
|
||||
if (unlikely(test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags)) &&
|
||||
q->rq_qos)
|
||||
if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos)
|
||||
__rq_qos_queue_depth_changed(q->rq_qos);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static int acpi_pci_irq_check_entry(acpi_handle handle, struct pci_dev *dev,
|
|||
* the IRQ value, which is hardwired to specific interrupt inputs on
|
||||
* the interrupt controller.
|
||||
*/
|
||||
pr_debug("%04x:%02x:%02x[%c] -> %s[%d]\n",
|
||||
pr_debug("%04x:%02x:%02x[%c] -> %s[%u]\n",
|
||||
entry->id.segment, entry->id.bus, entry->id.device,
|
||||
pin_name(entry->pin), prt->source, entry->index);
|
||||
|
||||
|
|
@ -384,7 +384,7 @@ static inline bool acpi_pci_irq_valid(struct pci_dev *dev, u8 pin)
|
|||
int acpi_pci_irq_enable(struct pci_dev *dev)
|
||||
{
|
||||
struct acpi_prt_entry *entry;
|
||||
int gsi;
|
||||
u32 gsi;
|
||||
u8 pin;
|
||||
int triggering = ACPI_LEVEL_SENSITIVE;
|
||||
/*
|
||||
|
|
@ -422,18 +422,21 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
rc = -ENODEV;
|
||||
|
||||
if (entry) {
|
||||
if (entry->link)
|
||||
gsi = acpi_pci_link_allocate_irq(entry->link,
|
||||
rc = acpi_pci_link_allocate_irq(entry->link,
|
||||
entry->index,
|
||||
&triggering, &polarity,
|
||||
&link);
|
||||
else
|
||||
&link, &gsi);
|
||||
else {
|
||||
gsi = entry->index;
|
||||
} else
|
||||
gsi = -1;
|
||||
rc = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (gsi < 0) {
|
||||
if (rc < 0) {
|
||||
/*
|
||||
* No IRQ known to the ACPI subsystem - maybe the BIOS /
|
||||
* driver reported one, then use it. Exit in any case.
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@ static int acpi_isa_irq_penalty[ACPI_MAX_ISA_IRQS] = {
|
|||
/* >IRQ15 */
|
||||
};
|
||||
|
||||
static int acpi_irq_pci_sharing_penalty(int irq)
|
||||
static int acpi_irq_pci_sharing_penalty(u32 irq)
|
||||
{
|
||||
struct acpi_pci_link *link;
|
||||
int penalty = 0;
|
||||
|
|
@ -474,7 +474,7 @@ static int acpi_irq_pci_sharing_penalty(int irq)
|
|||
return penalty;
|
||||
}
|
||||
|
||||
static int acpi_irq_get_penalty(int irq)
|
||||
static int acpi_irq_get_penalty(u32 irq)
|
||||
{
|
||||
int penalty = 0;
|
||||
|
||||
|
|
@ -528,7 +528,7 @@ static int acpi_irq_balance = -1; /* 0: static, 1: balance */
|
|||
static int acpi_pci_link_allocate(struct acpi_pci_link *link)
|
||||
{
|
||||
acpi_handle handle = link->device->handle;
|
||||
int irq;
|
||||
u32 irq;
|
||||
int i;
|
||||
|
||||
if (link->irq.initialized) {
|
||||
|
|
@ -598,44 +598,53 @@ static int acpi_pci_link_allocate(struct acpi_pci_link *link)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* acpi_pci_link_allocate_irq
|
||||
* success: return IRQ >= 0
|
||||
* failure: return -1
|
||||
/**
|
||||
* acpi_pci_link_allocate_irq(): Retrieve a link device GSI
|
||||
*
|
||||
* @handle: Handle for the link device
|
||||
* @index: GSI index
|
||||
* @triggering: pointer to store the GSI trigger
|
||||
* @polarity: pointer to store GSI polarity
|
||||
* @name: pointer to store link device name
|
||||
* @gsi: pointer to store GSI number
|
||||
*
|
||||
* Returns:
|
||||
* 0 on success with @triggering, @polarity, @name, @gsi initialized.
|
||||
* -ENODEV on failure
|
||||
*/
|
||||
int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
|
||||
int *polarity, char **name)
|
||||
int *polarity, char **name, u32 *gsi)
|
||||
{
|
||||
struct acpi_device *device = acpi_fetch_acpi_dev(handle);
|
||||
struct acpi_pci_link *link;
|
||||
|
||||
if (!device) {
|
||||
acpi_handle_err(handle, "Invalid link device\n");
|
||||
return -1;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
link = acpi_driver_data(device);
|
||||
if (!link) {
|
||||
acpi_handle_err(handle, "Invalid link context\n");
|
||||
return -1;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* TBD: Support multiple index (IRQ) entries per Link Device */
|
||||
if (index) {
|
||||
acpi_handle_err(handle, "Invalid index %d\n", index);
|
||||
return -1;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mutex_lock(&acpi_link_lock);
|
||||
if (acpi_pci_link_allocate(link)) {
|
||||
mutex_unlock(&acpi_link_lock);
|
||||
return -1;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!link->irq.active) {
|
||||
mutex_unlock(&acpi_link_lock);
|
||||
acpi_handle_err(handle, "Link active IRQ is 0!\n");
|
||||
return -1;
|
||||
return -ENODEV;
|
||||
}
|
||||
link->refcnt++;
|
||||
mutex_unlock(&acpi_link_lock);
|
||||
|
|
@ -647,7 +656,9 @@ int acpi_pci_link_allocate_irq(acpi_handle handle, int index, int *triggering,
|
|||
if (name)
|
||||
*name = acpi_device_bid(link->device);
|
||||
acpi_handle_debug(handle, "Link is referenced\n");
|
||||
return link->irq.active;
|
||||
*gsi = link->irq.active;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -727,8 +727,5 @@ fn drop(self: Pin<&mut Self>) {
|
|||
drop(mm);
|
||||
drop(page);
|
||||
|
||||
// SAFETY: We just unlocked the lru lock, but it should be locked when we return.
|
||||
unsafe { bindings::spin_lock(&raw mut (*lru).lock) };
|
||||
|
||||
LRU_REMOVED_ENTRY
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1587,7 +1587,8 @@ he_stop(struct he_dev *he_dev)
|
|||
he_dev->tbrq_base, he_dev->tbrq_phys);
|
||||
|
||||
if (he_dev->tpdrq_base)
|
||||
dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
|
||||
dma_free_coherent(&he_dev->pci_dev->dev,
|
||||
CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq),
|
||||
he_dev->tpdrq_base, he_dev->tpdrq_phys);
|
||||
|
||||
dma_pool_destroy(he_dev->tpd_pool);
|
||||
|
|
|
|||
|
|
@ -1225,16 +1225,28 @@ static int loop_clr_fd(struct loop_device *lo)
|
|||
}
|
||||
|
||||
static int
|
||||
loop_set_status(struct loop_device *lo, const struct loop_info64 *info)
|
||||
loop_set_status(struct loop_device *lo, blk_mode_t mode,
|
||||
struct block_device *bdev, const struct loop_info64 *info)
|
||||
{
|
||||
int err;
|
||||
bool partscan = false;
|
||||
bool size_changed = false;
|
||||
unsigned int memflags;
|
||||
|
||||
/*
|
||||
* If we don't hold exclusive handle for the device, upgrade to it
|
||||
* here to avoid changing device under exclusive owner.
|
||||
*/
|
||||
if (!(mode & BLK_OPEN_EXCL)) {
|
||||
err = bd_prepare_to_claim(bdev, loop_set_status, NULL);
|
||||
if (err)
|
||||
goto out_reread_partitions;
|
||||
}
|
||||
|
||||
err = mutex_lock_killable(&lo->lo_mutex);
|
||||
if (err)
|
||||
return err;
|
||||
goto out_abort_claiming;
|
||||
|
||||
if (lo->lo_state != Lo_bound) {
|
||||
err = -ENXIO;
|
||||
goto out_unlock;
|
||||
|
|
@ -1273,6 +1285,10 @@ loop_set_status(struct loop_device *lo, const struct loop_info64 *info)
|
|||
}
|
||||
out_unlock:
|
||||
mutex_unlock(&lo->lo_mutex);
|
||||
out_abort_claiming:
|
||||
if (!(mode & BLK_OPEN_EXCL))
|
||||
bd_abort_claiming(bdev, loop_set_status);
|
||||
out_reread_partitions:
|
||||
if (partscan)
|
||||
loop_reread_partitions(lo);
|
||||
|
||||
|
|
@ -1352,7 +1368,9 @@ loop_info64_to_old(const struct loop_info64 *info64, struct loop_info *info)
|
|||
}
|
||||
|
||||
static int
|
||||
loop_set_status_old(struct loop_device *lo, const struct loop_info __user *arg)
|
||||
loop_set_status_old(struct loop_device *lo, blk_mode_t mode,
|
||||
struct block_device *bdev,
|
||||
const struct loop_info __user *arg)
|
||||
{
|
||||
struct loop_info info;
|
||||
struct loop_info64 info64;
|
||||
|
|
@ -1360,17 +1378,19 @@ loop_set_status_old(struct loop_device *lo, const struct loop_info __user *arg)
|
|||
if (copy_from_user(&info, arg, sizeof (struct loop_info)))
|
||||
return -EFAULT;
|
||||
loop_info64_from_old(&info, &info64);
|
||||
return loop_set_status(lo, &info64);
|
||||
return loop_set_status(lo, mode, bdev, &info64);
|
||||
}
|
||||
|
||||
static int
|
||||
loop_set_status64(struct loop_device *lo, const struct loop_info64 __user *arg)
|
||||
loop_set_status64(struct loop_device *lo, blk_mode_t mode,
|
||||
struct block_device *bdev,
|
||||
const struct loop_info64 __user *arg)
|
||||
{
|
||||
struct loop_info64 info64;
|
||||
|
||||
if (copy_from_user(&info64, arg, sizeof (struct loop_info64)))
|
||||
return -EFAULT;
|
||||
return loop_set_status(lo, &info64);
|
||||
return loop_set_status(lo, mode, bdev, &info64);
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -1549,14 +1569,14 @@ static int lo_ioctl(struct block_device *bdev, blk_mode_t mode,
|
|||
case LOOP_SET_STATUS:
|
||||
err = -EPERM;
|
||||
if ((mode & BLK_OPEN_WRITE) || capable(CAP_SYS_ADMIN))
|
||||
err = loop_set_status_old(lo, argp);
|
||||
err = loop_set_status_old(lo, mode, bdev, argp);
|
||||
break;
|
||||
case LOOP_GET_STATUS:
|
||||
return loop_get_status_old(lo, argp);
|
||||
case LOOP_SET_STATUS64:
|
||||
err = -EPERM;
|
||||
if ((mode & BLK_OPEN_WRITE) || capable(CAP_SYS_ADMIN))
|
||||
err = loop_set_status64(lo, argp);
|
||||
err = loop_set_status64(lo, mode, bdev, argp);
|
||||
break;
|
||||
case LOOP_GET_STATUS64:
|
||||
return loop_get_status64(lo, argp);
|
||||
|
|
@ -1650,8 +1670,9 @@ loop_info64_to_compat(const struct loop_info64 *info64,
|
|||
}
|
||||
|
||||
static int
|
||||
loop_set_status_compat(struct loop_device *lo,
|
||||
const struct compat_loop_info __user *arg)
|
||||
loop_set_status_compat(struct loop_device *lo, blk_mode_t mode,
|
||||
struct block_device *bdev,
|
||||
const struct compat_loop_info __user *arg)
|
||||
{
|
||||
struct loop_info64 info64;
|
||||
int ret;
|
||||
|
|
@ -1659,7 +1680,7 @@ loop_set_status_compat(struct loop_device *lo,
|
|||
ret = loop_info64_from_compat(arg, &info64);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return loop_set_status(lo, &info64);
|
||||
return loop_set_status(lo, mode, bdev, &info64);
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -1685,7 +1706,7 @@ static int lo_compat_ioctl(struct block_device *bdev, blk_mode_t mode,
|
|||
|
||||
switch(cmd) {
|
||||
case LOOP_SET_STATUS:
|
||||
err = loop_set_status_compat(lo,
|
||||
err = loop_set_status_compat(lo, mode, bdev,
|
||||
(const struct compat_loop_info __user *)arg);
|
||||
break;
|
||||
case LOOP_GET_STATUS:
|
||||
|
|
|
|||
|
|
@ -255,20 +255,6 @@ static inline struct request *__ublk_check_and_get_req(struct ublk_device *ub,
|
|||
u16 q_id, u16 tag, struct ublk_io *io, size_t offset);
|
||||
static inline unsigned int ublk_req_build_flags(struct request *req);
|
||||
|
||||
static void ublk_partition_scan_work(struct work_struct *work)
|
||||
{
|
||||
struct ublk_device *ub =
|
||||
container_of(work, struct ublk_device, partition_scan_work);
|
||||
|
||||
if (WARN_ON_ONCE(!test_and_clear_bit(GD_SUPPRESS_PART_SCAN,
|
||||
&ub->ub_disk->state)))
|
||||
return;
|
||||
|
||||
mutex_lock(&ub->ub_disk->open_mutex);
|
||||
bdev_disk_changed(ub->ub_disk, false);
|
||||
mutex_unlock(&ub->ub_disk->open_mutex);
|
||||
}
|
||||
|
||||
static inline struct ublksrv_io_desc *
|
||||
ublk_get_iod(const struct ublk_queue *ubq, unsigned tag)
|
||||
{
|
||||
|
|
@ -1597,6 +1583,27 @@ static void ublk_put_disk(struct gendisk *disk)
|
|||
put_device(disk_to_dev(disk));
|
||||
}
|
||||
|
||||
static void ublk_partition_scan_work(struct work_struct *work)
|
||||
{
|
||||
struct ublk_device *ub =
|
||||
container_of(work, struct ublk_device, partition_scan_work);
|
||||
/* Hold disk reference to prevent UAF during concurrent teardown */
|
||||
struct gendisk *disk = ublk_get_disk(ub);
|
||||
|
||||
if (!disk)
|
||||
return;
|
||||
|
||||
if (WARN_ON_ONCE(!test_and_clear_bit(GD_SUPPRESS_PART_SCAN,
|
||||
&disk->state)))
|
||||
goto out;
|
||||
|
||||
mutex_lock(&disk->open_mutex);
|
||||
bdev_disk_changed(disk, false);
|
||||
mutex_unlock(&disk->open_mutex);
|
||||
out:
|
||||
ublk_put_disk(disk);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use this function to ensure that ->canceling is consistently set for
|
||||
* the device and all queues. Do not set these flags directly.
|
||||
|
|
@ -2041,7 +2048,7 @@ static void ublk_stop_dev(struct ublk_device *ub)
|
|||
mutex_lock(&ub->mutex);
|
||||
ublk_stop_dev_unlocked(ub);
|
||||
mutex_unlock(&ub->mutex);
|
||||
flush_work(&ub->partition_scan_work);
|
||||
cancel_work_sync(&ub->partition_scan_work);
|
||||
ublk_cancel_dev(ub);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1192,6 +1192,7 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
|
|||
{
|
||||
struct counter_device *counter = private;
|
||||
struct quad8 *const priv = counter_priv(counter);
|
||||
struct device *dev = counter->parent;
|
||||
unsigned int status;
|
||||
unsigned long irq_status;
|
||||
unsigned long channel;
|
||||
|
|
@ -1200,8 +1201,11 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
|
|||
int ret;
|
||||
|
||||
ret = regmap_read(priv->map, QUAD8_INTERRUPT_STATUS, &status);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret) {
|
||||
dev_WARN_ONCE(dev, true,
|
||||
"Attempt to read Interrupt Status Register failed: %d\n", ret);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
if (!status)
|
||||
return IRQ_NONE;
|
||||
|
||||
|
|
@ -1223,8 +1227,9 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
|
|||
break;
|
||||
default:
|
||||
/* should never reach this path */
|
||||
WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
|
||||
flg_pins, channel);
|
||||
dev_WARN_ONCE(dev, true,
|
||||
"invalid interrupt trigger function %u configured for channel %lu\n",
|
||||
flg_pins, channel);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -1232,8 +1237,11 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
|
|||
}
|
||||
|
||||
ret = regmap_write(priv->map, QUAD8_CHANNEL_OPERATION, CLEAR_PENDING_INTERRUPTS);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret) {
|
||||
dev_WARN_ONCE(dev, true,
|
||||
"Attempt to clear pending interrupts by writing to Channel Operation Register failed: %d\n", ret);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -229,8 +229,7 @@ static int interrupt_cnt_probe(struct platform_device *pdev)
|
|||
|
||||
irq_set_status_flags(priv->irq, IRQ_NOAUTOEN);
|
||||
ret = devm_request_irq(dev, priv->irq, interrupt_cnt_isr,
|
||||
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
|
||||
dev_name(dev), counter);
|
||||
IRQF_TRIGGER_RISING, dev_name(dev), counter);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -41,8 +41,6 @@ static pci_ers_result_t adf_error_detected(struct pci_dev *pdev,
|
|||
adf_error_notifier(accel_dev);
|
||||
adf_pf2vf_notify_fatal_error(accel_dev);
|
||||
adf_dev_restarting_notify(accel_dev);
|
||||
adf_pf2vf_notify_restarting(accel_dev);
|
||||
adf_pf2vf_wait_for_restarting_complete(accel_dev);
|
||||
pci_clear_master(pdev);
|
||||
adf_dev_down(accel_dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
|
|
@ -241,23 +242,17 @@ static int it87_gpio_direction_out(struct gpio_chip *chip,
|
|||
mask = 1 << (gpio_num % 8);
|
||||
group = (gpio_num / 8);
|
||||
|
||||
spin_lock(&it87_gpio->lock);
|
||||
guard(spinlock)(&it87_gpio->lock);
|
||||
|
||||
rc = superio_enter();
|
||||
if (rc)
|
||||
goto exit;
|
||||
return rc;
|
||||
|
||||
/* set the output enable bit */
|
||||
superio_set_mask(mask, group + it87_gpio->output_base);
|
||||
|
||||
rc = it87_gpio_set(chip, gpio_num, val);
|
||||
if (rc)
|
||||
goto exit;
|
||||
|
||||
superio_exit();
|
||||
|
||||
exit:
|
||||
spin_unlock(&it87_gpio->lock);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -548,6 +548,13 @@ static void gpio_mpsse_ida_remove(void *data)
|
|||
ida_free(&gpio_mpsse_ida, priv->id);
|
||||
}
|
||||
|
||||
static void gpio_mpsse_usb_put_dev(void *data)
|
||||
{
|
||||
struct mpsse_priv *priv = data;
|
||||
|
||||
usb_put_dev(priv->udev);
|
||||
}
|
||||
|
||||
static int mpsse_init_valid_mask(struct gpio_chip *chip,
|
||||
unsigned long *valid_mask,
|
||||
unsigned int ngpios)
|
||||
|
|
@ -592,6 +599,10 @@ static int gpio_mpsse_probe(struct usb_interface *interface,
|
|||
INIT_LIST_HEAD(&priv->workers);
|
||||
|
||||
priv->udev = usb_get_dev(interface_to_usbdev(interface));
|
||||
err = devm_add_action_or_reset(dev, gpio_mpsse_usb_put_dev, priv);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
priv->intf = interface;
|
||||
priv->intf_id = interface->cur_altsetting->desc.bInterfaceNumber;
|
||||
|
||||
|
|
@ -713,7 +724,6 @@ static void gpio_mpsse_disconnect(struct usb_interface *intf)
|
|||
|
||||
priv->intf = NULL;
|
||||
usb_set_intfdata(intf, NULL);
|
||||
usb_put_dev(priv->udev);
|
||||
}
|
||||
|
||||
static struct usb_driver gpio_mpsse_driver = {
|
||||
|
|
|
|||
|
|
@ -943,14 +943,35 @@ static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pendin
|
|||
DECLARE_BITMAP(old_stat, MAX_LINE);
|
||||
DECLARE_BITMAP(cur_stat, MAX_LINE);
|
||||
DECLARE_BITMAP(new_stat, MAX_LINE);
|
||||
DECLARE_BITMAP(int_stat, MAX_LINE);
|
||||
DECLARE_BITMAP(trigger, MAX_LINE);
|
||||
DECLARE_BITMAP(edges, MAX_LINE);
|
||||
int ret;
|
||||
|
||||
if (chip->driver_data & PCA_PCAL) {
|
||||
/* Read INT_STAT before it is cleared by the input-port read. */
|
||||
ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, int_stat);
|
||||
if (ret)
|
||||
return false;
|
||||
}
|
||||
|
||||
ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
if (chip->driver_data & PCA_PCAL) {
|
||||
/* Detect short pulses via INT_STAT. */
|
||||
bitmap_and(trigger, int_stat, chip->irq_mask, gc->ngpio);
|
||||
|
||||
/* Apply filter for rising/falling edge selection. */
|
||||
bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
|
||||
cur_stat, gc->ngpio);
|
||||
|
||||
bitmap_and(int_stat, new_stat, trigger, gc->ngpio);
|
||||
} else {
|
||||
bitmap_zero(int_stat, gc->ngpio);
|
||||
}
|
||||
|
||||
/* Remove output pins from the equation */
|
||||
pca953x_read_regs(chip, chip->regs->direction, reg_direction);
|
||||
|
||||
|
|
@ -964,7 +985,8 @@ static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pendin
|
|||
|
||||
if (bitmap_empty(chip->irq_trig_level_high, gc->ngpio) &&
|
||||
bitmap_empty(chip->irq_trig_level_low, gc->ngpio)) {
|
||||
if (bitmap_empty(trigger, gc->ngpio))
|
||||
if (bitmap_empty(trigger, gc->ngpio) &&
|
||||
bitmap_empty(int_stat, gc->ngpio))
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -972,6 +994,7 @@ static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pendin
|
|||
bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
|
||||
bitmap_or(edges, old_stat, cur_stat, gc->ngpio);
|
||||
bitmap_and(pending, edges, trigger, gc->ngpio);
|
||||
bitmap_or(pending, pending, int_stat, gc->ngpio);
|
||||
|
||||
bitmap_and(cur_stat, new_stat, chip->irq_trig_level_high, gc->ngpio);
|
||||
bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio);
|
||||
|
|
|
|||
|
|
@ -593,6 +593,7 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
|
|||
gc->ngpio = bank->nr_pins;
|
||||
gc->label = bank->name;
|
||||
gc->parent = bank->dev;
|
||||
gc->can_sleep = true;
|
||||
|
||||
ret = gpiochip_add_data(gc, bank);
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -38,8 +38,10 @@ struct gpio_shared_ref {
|
|||
int dev_id;
|
||||
/* Protects the auxiliary device struct and the lookup table. */
|
||||
struct mutex lock;
|
||||
struct lock_class_key lock_key;
|
||||
struct auxiliary_device adev;
|
||||
struct gpiod_lookup_table *lookup;
|
||||
bool is_reset_gpio;
|
||||
};
|
||||
|
||||
/* Represents a single GPIO pin. */
|
||||
|
|
@ -76,6 +78,60 @@ gpio_shared_find_entry(struct fwnode_handle *controller_node,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static struct gpio_shared_ref *gpio_shared_make_ref(struct fwnode_handle *fwnode,
|
||||
const char *con_id,
|
||||
enum gpiod_flags flags)
|
||||
{
|
||||
char *con_id_cpy __free(kfree) = NULL;
|
||||
|
||||
struct gpio_shared_ref *ref __free(kfree) = kzalloc(sizeof(*ref), GFP_KERNEL);
|
||||
if (!ref)
|
||||
return NULL;
|
||||
|
||||
if (con_id) {
|
||||
con_id_cpy = kstrdup(con_id, GFP_KERNEL);
|
||||
if (!con_id_cpy)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ref->dev_id = ida_alloc(&gpio_shared_ida, GFP_KERNEL);
|
||||
if (ref->dev_id < 0)
|
||||
return NULL;
|
||||
|
||||
ref->flags = flags;
|
||||
ref->con_id = no_free_ptr(con_id_cpy);
|
||||
ref->fwnode = fwnode;
|
||||
lockdep_register_key(&ref->lock_key);
|
||||
mutex_init_with_key(&ref->lock, &ref->lock_key);
|
||||
|
||||
return no_free_ptr(ref);
|
||||
}
|
||||
|
||||
static int gpio_shared_setup_reset_proxy(struct gpio_shared_entry *entry,
|
||||
enum gpiod_flags flags)
|
||||
{
|
||||
struct gpio_shared_ref *ref;
|
||||
|
||||
list_for_each_entry(ref, &entry->refs, list) {
|
||||
if (ref->is_reset_gpio)
|
||||
/* Already set-up. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
ref = gpio_shared_make_ref(NULL, "reset", flags);
|
||||
if (!ref)
|
||||
return -ENOMEM;
|
||||
|
||||
ref->is_reset_gpio = true;
|
||||
|
||||
list_add_tail(&ref->list, &entry->refs);
|
||||
|
||||
pr_debug("Created a secondary shared GPIO reference for potential reset-gpio device for GPIO %u at %s\n",
|
||||
entry->offset, fwnode_get_name(entry->fwnode));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Handle all special nodes that we should ignore. */
|
||||
static bool gpio_shared_of_node_ignore(struct device_node *node)
|
||||
{
|
||||
|
|
@ -106,6 +162,7 @@ static int gpio_shared_of_traverse(struct device_node *curr)
|
|||
size_t con_id_len, suffix_len;
|
||||
struct fwnode_handle *fwnode;
|
||||
struct of_phandle_args args;
|
||||
struct gpio_shared_ref *ref;
|
||||
struct property *prop;
|
||||
unsigned int offset;
|
||||
const char *suffix;
|
||||
|
|
@ -138,6 +195,7 @@ static int gpio_shared_of_traverse(struct device_node *curr)
|
|||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct device_node *np __free(device_node) = NULL;
|
||||
char *con_id __free(kfree) = NULL;
|
||||
|
||||
ret = of_parse_phandle_with_args(curr, prop->name,
|
||||
"#gpio-cells", i,
|
||||
|
|
@ -182,15 +240,6 @@ static int gpio_shared_of_traverse(struct device_node *curr)
|
|||
list_add_tail(&entry->list, &gpio_shared_list);
|
||||
}
|
||||
|
||||
struct gpio_shared_ref *ref __free(kfree) =
|
||||
kzalloc(sizeof(*ref), GFP_KERNEL);
|
||||
if (!ref)
|
||||
return -ENOMEM;
|
||||
|
||||
ref->fwnode = fwnode_handle_get(of_fwnode_handle(curr));
|
||||
ref->flags = args.args[1];
|
||||
mutex_init(&ref->lock);
|
||||
|
||||
if (strends(prop->name, "gpios"))
|
||||
suffix = "-gpios";
|
||||
else if (strends(prop->name, "gpio"))
|
||||
|
|
@ -202,27 +251,32 @@ static int gpio_shared_of_traverse(struct device_node *curr)
|
|||
|
||||
/* We only set con_id if there's actually one. */
|
||||
if (strcmp(prop->name, "gpios") && strcmp(prop->name, "gpio")) {
|
||||
ref->con_id = kstrdup(prop->name, GFP_KERNEL);
|
||||
if (!ref->con_id)
|
||||
con_id = kstrdup(prop->name, GFP_KERNEL);
|
||||
if (!con_id)
|
||||
return -ENOMEM;
|
||||
|
||||
con_id_len = strlen(ref->con_id);
|
||||
con_id_len = strlen(con_id);
|
||||
suffix_len = strlen(suffix);
|
||||
|
||||
ref->con_id[con_id_len - suffix_len] = '\0';
|
||||
con_id[con_id_len - suffix_len] = '\0';
|
||||
}
|
||||
|
||||
ref->dev_id = ida_alloc(&gpio_shared_ida, GFP_KERNEL);
|
||||
if (ref->dev_id < 0) {
|
||||
kfree(ref->con_id);
|
||||
ref = gpio_shared_make_ref(fwnode_handle_get(of_fwnode_handle(curr)),
|
||||
con_id, args.args[1]);
|
||||
if (!ref)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (!list_empty(&entry->refs))
|
||||
pr_debug("GPIO %u at %s is shared by multiple firmware nodes\n",
|
||||
entry->offset, fwnode_get_name(entry->fwnode));
|
||||
|
||||
list_add_tail(&no_free_ptr(ref)->list, &entry->refs);
|
||||
list_add_tail(&ref->list, &entry->refs);
|
||||
|
||||
if (strcmp(prop->name, "reset-gpios") == 0) {
|
||||
ret = gpio_shared_setup_reset_proxy(entry, args.args[1]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -306,20 +360,16 @@ static bool gpio_shared_dev_is_reset_gpio(struct device *consumer,
|
|||
struct fwnode_handle *reset_fwnode = dev_fwnode(consumer);
|
||||
struct fwnode_reference_args ref_args, aux_args;
|
||||
struct device *parent = consumer->parent;
|
||||
struct gpio_shared_ref *real_ref;
|
||||
bool match;
|
||||
int ret;
|
||||
|
||||
lockdep_assert_held(&ref->lock);
|
||||
|
||||
/* The reset-gpio device must have a parent AND a firmware node. */
|
||||
if (!parent || !reset_fwnode)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* FIXME: use device_is_compatible() once the reset-gpio drivers gains
|
||||
* a compatible string which it currently does not have.
|
||||
*/
|
||||
if (!strstarts(dev_name(consumer), "reset.gpio."))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Parent of the reset-gpio auxiliary device is the GPIO chip whose
|
||||
* fwnode we stored in the entry structure.
|
||||
|
|
@ -328,33 +378,61 @@ static bool gpio_shared_dev_is_reset_gpio(struct device *consumer,
|
|||
return false;
|
||||
|
||||
/*
|
||||
* The device associated with the shared reference's firmware node is
|
||||
* the consumer of the reset control exposed by the reset-gpio device.
|
||||
* It must have a "reset-gpios" property that's referencing the entry's
|
||||
* firmware node.
|
||||
*
|
||||
* The reference args must agree between the real consumer and the
|
||||
* auxiliary reset-gpio device.
|
||||
* Now we need to find the actual pin we want to assign to this
|
||||
* reset-gpio device. To that end: iterate over the list of references
|
||||
* of this entry and see if there's one, whose reset-gpios property's
|
||||
* arguments match the ones from this consumer's node.
|
||||
*/
|
||||
ret = fwnode_property_get_reference_args(ref->fwnode, "reset-gpios",
|
||||
NULL, 2, 0, &ref_args);
|
||||
if (ret)
|
||||
return false;
|
||||
list_for_each_entry(real_ref, &entry->refs, list) {
|
||||
if (real_ref == ref)
|
||||
continue;
|
||||
|
||||
guard(mutex)(&real_ref->lock);
|
||||
|
||||
if (!real_ref->fwnode)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* The device associated with the shared reference's firmware
|
||||
* node is the consumer of the reset control exposed by the
|
||||
* reset-gpio device. It must have a "reset-gpios" property
|
||||
* that's referencing the entry's firmware node.
|
||||
*
|
||||
* The reference args must agree between the real consumer and
|
||||
* the auxiliary reset-gpio device.
|
||||
*/
|
||||
ret = fwnode_property_get_reference_args(real_ref->fwnode,
|
||||
"reset-gpios",
|
||||
NULL, 2, 0, &ref_args);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
ret = fwnode_property_get_reference_args(reset_fwnode, "reset-gpios",
|
||||
NULL, 2, 0, &aux_args);
|
||||
if (ret) {
|
||||
fwnode_handle_put(ref_args.fwnode);
|
||||
continue;
|
||||
}
|
||||
|
||||
match = ((ref_args.fwnode == entry->fwnode) &&
|
||||
(aux_args.fwnode == entry->fwnode) &&
|
||||
(ref_args.args[0] == aux_args.args[0]));
|
||||
|
||||
ret = fwnode_property_get_reference_args(reset_fwnode, "reset-gpios",
|
||||
NULL, 2, 0, &aux_args);
|
||||
if (ret) {
|
||||
fwnode_handle_put(ref_args.fwnode);
|
||||
return false;
|
||||
fwnode_handle_put(aux_args.fwnode);
|
||||
|
||||
if (!match)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Reuse the fwnode of the real device, next time we'll use it
|
||||
* in the normal path.
|
||||
*/
|
||||
ref->fwnode = fwnode_handle_get(reset_fwnode);
|
||||
return true;
|
||||
}
|
||||
|
||||
match = ((ref_args.fwnode == entry->fwnode) &&
|
||||
(aux_args.fwnode == entry->fwnode) &&
|
||||
(ref_args.args[0] == aux_args.args[0]));
|
||||
|
||||
fwnode_handle_put(ref_args.fwnode);
|
||||
fwnode_handle_put(aux_args.fwnode);
|
||||
return match;
|
||||
return false;
|
||||
}
|
||||
#else
|
||||
static bool gpio_shared_dev_is_reset_gpio(struct device *consumer,
|
||||
|
|
@ -365,25 +443,34 @@ static bool gpio_shared_dev_is_reset_gpio(struct device *consumer,
|
|||
}
|
||||
#endif /* CONFIG_RESET_GPIO */
|
||||
|
||||
int gpio_shared_add_proxy_lookup(struct device *consumer, unsigned long lflags)
|
||||
int gpio_shared_add_proxy_lookup(struct device *consumer, const char *con_id,
|
||||
unsigned long lflags)
|
||||
{
|
||||
const char *dev_id = dev_name(consumer);
|
||||
struct gpiod_lookup_table *lookup;
|
||||
struct gpio_shared_entry *entry;
|
||||
struct gpio_shared_ref *ref;
|
||||
|
||||
struct gpiod_lookup_table *lookup __free(kfree) =
|
||||
kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
|
||||
if (!lookup)
|
||||
return -ENOMEM;
|
||||
|
||||
list_for_each_entry(entry, &gpio_shared_list, list) {
|
||||
list_for_each_entry(ref, &entry->refs, list) {
|
||||
if (!device_match_fwnode(consumer, ref->fwnode) &&
|
||||
!gpio_shared_dev_is_reset_gpio(consumer, entry, ref))
|
||||
continue;
|
||||
|
||||
guard(mutex)(&ref->lock);
|
||||
|
||||
/*
|
||||
* FIXME: use device_is_compatible() once the reset-gpio
|
||||
* drivers gains a compatible string which it currently
|
||||
* does not have.
|
||||
*/
|
||||
if (!ref->fwnode && strstarts(dev_name(consumer), "reset.gpio.")) {
|
||||
if (!gpio_shared_dev_is_reset_gpio(consumer, entry, ref))
|
||||
continue;
|
||||
} else if (!device_match_fwnode(consumer, ref->fwnode)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((!con_id && ref->con_id) || (con_id && !ref->con_id) ||
|
||||
(con_id && ref->con_id && strcmp(con_id, ref->con_id) != 0))
|
||||
continue;
|
||||
|
||||
/* We've already done that on a previous request. */
|
||||
if (ref->lookup)
|
||||
return 0;
|
||||
|
|
@ -395,6 +482,10 @@ int gpio_shared_add_proxy_lookup(struct device *consumer, unsigned long lflags)
|
|||
if (!key)
|
||||
return -ENOMEM;
|
||||
|
||||
lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
|
||||
if (!lookup)
|
||||
return -ENOMEM;
|
||||
|
||||
pr_debug("Adding machine lookup entry for a shared GPIO for consumer %s, with key '%s' and con_id '%s'\n",
|
||||
dev_id, key, ref->con_id ?: "none");
|
||||
|
||||
|
|
@ -402,7 +493,7 @@ int gpio_shared_add_proxy_lookup(struct device *consumer, unsigned long lflags)
|
|||
lookup->table[0] = GPIO_LOOKUP(no_free_ptr(key), 0,
|
||||
ref->con_id, lflags);
|
||||
|
||||
ref->lookup = no_free_ptr(lookup);
|
||||
ref->lookup = lookup;
|
||||
gpiod_add_lookup_table(ref->lookup);
|
||||
|
||||
return 0;
|
||||
|
|
@ -466,8 +557,9 @@ int gpio_device_setup_shared(struct gpio_device *gdev)
|
|||
entry->offset, gpio_device_get_label(gdev));
|
||||
|
||||
list_for_each_entry(ref, &entry->refs, list) {
|
||||
pr_debug("Setting up a shared GPIO entry for %s\n",
|
||||
fwnode_get_name(ref->fwnode));
|
||||
pr_debug("Setting up a shared GPIO entry for %s (con_id: '%s')\n",
|
||||
fwnode_get_name(ref->fwnode) ?: "(no fwnode)",
|
||||
ref->con_id ?: "(none)");
|
||||
|
||||
ret = gpio_shared_make_adev(gdev, entry, ref);
|
||||
if (ret)
|
||||
|
|
@ -487,15 +579,6 @@ void gpio_device_teardown_shared(struct gpio_device *gdev)
|
|||
if (!device_match_fwnode(&gdev->dev, entry->fwnode))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* For some reason if we call synchronize_srcu() in GPIO core,
|
||||
* descent here and take this mutex and then recursively call
|
||||
* synchronize_srcu() again from gpiochip_remove() (which is
|
||||
* totally fine) called after gpio_shared_remove_adev(),
|
||||
* lockdep prints a false positive deadlock splat. Disable
|
||||
* lockdep here.
|
||||
*/
|
||||
lockdep_off();
|
||||
list_for_each_entry(ref, &entry->refs, list) {
|
||||
guard(mutex)(&ref->lock);
|
||||
|
||||
|
|
@ -508,7 +591,6 @@ void gpio_device_teardown_shared(struct gpio_device *gdev)
|
|||
|
||||
gpio_shared_remove_adev(&ref->adev);
|
||||
}
|
||||
lockdep_on();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -604,6 +686,7 @@ static void gpio_shared_drop_ref(struct gpio_shared_ref *ref)
|
|||
{
|
||||
list_del(&ref->list);
|
||||
mutex_destroy(&ref->lock);
|
||||
lockdep_unregister_key(&ref->lock_key);
|
||||
kfree(ref->con_id);
|
||||
ida_free(&gpio_shared_ida, ref->dev_id);
|
||||
fwnode_handle_put(ref->fwnode);
|
||||
|
|
@ -635,12 +718,38 @@ static void __init gpio_shared_teardown(void)
|
|||
}
|
||||
}
|
||||
|
||||
static bool gpio_shared_entry_is_really_shared(struct gpio_shared_entry *entry)
|
||||
{
|
||||
size_t num_nodes = list_count_nodes(&entry->refs);
|
||||
struct gpio_shared_ref *ref;
|
||||
|
||||
if (num_nodes <= 1)
|
||||
return false;
|
||||
|
||||
if (num_nodes > 2)
|
||||
return true;
|
||||
|
||||
/* Exactly two references: */
|
||||
list_for_each_entry(ref, &entry->refs, list) {
|
||||
/*
|
||||
* Corner-case: the second reference comes from the potential
|
||||
* reset-gpio instance. However, this pin is not really shared
|
||||
* as it would have three references in this case. Avoid
|
||||
* creating unnecessary proxies.
|
||||
*/
|
||||
if (ref->is_reset_gpio)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void gpio_shared_free_exclusive(void)
|
||||
{
|
||||
struct gpio_shared_entry *entry, *epos;
|
||||
|
||||
list_for_each_entry_safe(entry, epos, &gpio_shared_list, list) {
|
||||
if (list_count_nodes(&entry->refs) > 1)
|
||||
if (gpio_shared_entry_is_really_shared(entry))
|
||||
continue;
|
||||
|
||||
gpio_shared_drop_ref(list_first_entry(&entry->refs,
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ struct device;
|
|||
|
||||
int gpio_device_setup_shared(struct gpio_device *gdev);
|
||||
void gpio_device_teardown_shared(struct gpio_device *gdev);
|
||||
int gpio_shared_add_proxy_lookup(struct device *consumer, unsigned long lflags);
|
||||
int gpio_shared_add_proxy_lookup(struct device *consumer, const char *con_id,
|
||||
unsigned long lflags);
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -28,6 +29,7 @@ static inline int gpio_device_setup_shared(struct gpio_device *gdev)
|
|||
static inline void gpio_device_teardown_shared(struct gpio_device *gdev) { }
|
||||
|
||||
static inline int gpio_shared_add_proxy_lookup(struct device *consumer,
|
||||
const char *con_id,
|
||||
unsigned long lflags)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1105,6 +1105,18 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
gdev->ngpio = gc->ngpio;
|
||||
gdev->can_sleep = gc->can_sleep;
|
||||
|
||||
rwlock_init(&gdev->line_state_lock);
|
||||
RAW_INIT_NOTIFIER_HEAD(&gdev->line_state_notifier);
|
||||
BLOCKING_INIT_NOTIFIER_HEAD(&gdev->device_notifier);
|
||||
|
||||
ret = init_srcu_struct(&gdev->srcu);
|
||||
if (ret)
|
||||
goto err_free_label;
|
||||
|
||||
ret = init_srcu_struct(&gdev->desc_srcu);
|
||||
if (ret)
|
||||
goto err_cleanup_gdev_srcu;
|
||||
|
||||
scoped_guard(mutex, &gpio_devices_lock) {
|
||||
/*
|
||||
* TODO: this allocates a Linux GPIO number base in the global
|
||||
|
|
@ -1119,7 +1131,7 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
if (base < 0) {
|
||||
ret = base;
|
||||
base = 0;
|
||||
goto err_free_label;
|
||||
goto err_cleanup_desc_srcu;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1139,22 +1151,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
ret = gpiodev_add_to_list_unlocked(gdev);
|
||||
if (ret) {
|
||||
gpiochip_err(gc, "GPIO integer space overlap, cannot add chip\n");
|
||||
goto err_free_label;
|
||||
goto err_cleanup_desc_srcu;
|
||||
}
|
||||
}
|
||||
|
||||
rwlock_init(&gdev->line_state_lock);
|
||||
RAW_INIT_NOTIFIER_HEAD(&gdev->line_state_notifier);
|
||||
BLOCKING_INIT_NOTIFIER_HEAD(&gdev->device_notifier);
|
||||
|
||||
ret = init_srcu_struct(&gdev->srcu);
|
||||
if (ret)
|
||||
goto err_remove_from_list;
|
||||
|
||||
ret = init_srcu_struct(&gdev->desc_srcu);
|
||||
if (ret)
|
||||
goto err_cleanup_gdev_srcu;
|
||||
|
||||
#ifdef CONFIG_PINCTRL
|
||||
INIT_LIST_HEAD(&gdev->pin_ranges);
|
||||
#endif
|
||||
|
|
@ -1164,11 +1164,11 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
|
||||
ret = gpiochip_set_names(gc);
|
||||
if (ret)
|
||||
goto err_cleanup_desc_srcu;
|
||||
goto err_remove_from_list;
|
||||
|
||||
ret = gpiochip_init_valid_mask(gc);
|
||||
if (ret)
|
||||
goto err_cleanup_desc_srcu;
|
||||
goto err_remove_from_list;
|
||||
|
||||
for (desc_index = 0; desc_index < gc->ngpio; desc_index++) {
|
||||
struct gpio_desc *desc = &gdev->descs[desc_index];
|
||||
|
|
@ -1248,10 +1248,6 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
of_gpiochip_remove(gc);
|
||||
err_free_valid_mask:
|
||||
gpiochip_free_valid_mask(gc);
|
||||
err_cleanup_desc_srcu:
|
||||
cleanup_srcu_struct(&gdev->desc_srcu);
|
||||
err_cleanup_gdev_srcu:
|
||||
cleanup_srcu_struct(&gdev->srcu);
|
||||
err_remove_from_list:
|
||||
scoped_guard(mutex, &gpio_devices_lock)
|
||||
list_del_rcu(&gdev->list);
|
||||
|
|
@ -1261,6 +1257,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
|||
gpio_device_put(gdev);
|
||||
goto err_print_message;
|
||||
}
|
||||
err_cleanup_desc_srcu:
|
||||
cleanup_srcu_struct(&gdev->desc_srcu);
|
||||
err_cleanup_gdev_srcu:
|
||||
cleanup_srcu_struct(&gdev->srcu);
|
||||
err_free_label:
|
||||
kfree_const(gdev->label);
|
||||
err_free_descs:
|
||||
|
|
@ -4508,45 +4508,41 @@ void gpiod_remove_hogs(struct gpiod_hog *hogs)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(gpiod_remove_hogs);
|
||||
|
||||
static struct gpiod_lookup_table *gpiod_find_lookup_table(struct device *dev)
|
||||
static bool gpiod_match_lookup_table(struct device *dev,
|
||||
const struct gpiod_lookup_table *table)
|
||||
{
|
||||
const char *dev_id = dev ? dev_name(dev) : NULL;
|
||||
struct gpiod_lookup_table *table;
|
||||
|
||||
list_for_each_entry(table, &gpio_lookup_list, list) {
|
||||
if (table->dev_id && dev_id) {
|
||||
/*
|
||||
* Valid strings on both ends, must be identical to have
|
||||
* a match
|
||||
*/
|
||||
if (!strcmp(table->dev_id, dev_id))
|
||||
return table;
|
||||
} else {
|
||||
/*
|
||||
* One of the pointers is NULL, so both must be to have
|
||||
* a match
|
||||
*/
|
||||
if (dev_id == table->dev_id)
|
||||
return table;
|
||||
}
|
||||
lockdep_assert_held(&gpio_lookup_lock);
|
||||
|
||||
if (table->dev_id && dev_id) {
|
||||
/*
|
||||
* Valid strings on both ends, must be identical to have
|
||||
* a match
|
||||
*/
|
||||
if (!strcmp(table->dev_id, dev_id))
|
||||
return true;
|
||||
} else {
|
||||
/*
|
||||
* One of the pointers is NULL, so both must be to have
|
||||
* a match
|
||||
*/
|
||||
if (dev_id == table->dev_id)
|
||||
return true;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
return false;
|
||||
}
|
||||
|
||||
static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
|
||||
unsigned int idx, unsigned long *flags)
|
||||
static struct gpio_desc *gpio_desc_table_match(struct device *dev, const char *con_id,
|
||||
unsigned int idx, unsigned long *flags,
|
||||
struct gpiod_lookup_table *table)
|
||||
{
|
||||
struct gpio_desc *desc = ERR_PTR(-ENOENT);
|
||||
struct gpiod_lookup_table *table;
|
||||
struct gpio_desc *desc;
|
||||
struct gpiod_lookup *p;
|
||||
struct gpio_chip *gc;
|
||||
|
||||
guard(mutex)(&gpio_lookup_lock);
|
||||
|
||||
table = gpiod_find_lookup_table(dev);
|
||||
if (!table)
|
||||
return desc;
|
||||
lockdep_assert_held(&gpio_lookup_lock);
|
||||
|
||||
for (p = &table->table[0]; p->key; p++) {
|
||||
/* idx must always match exactly */
|
||||
|
|
@ -4600,7 +4596,30 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
|
|||
return desc;
|
||||
}
|
||||
|
||||
return desc;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
|
||||
unsigned int idx, unsigned long *flags)
|
||||
{
|
||||
struct gpiod_lookup_table *table;
|
||||
struct gpio_desc *desc;
|
||||
|
||||
guard(mutex)(&gpio_lookup_lock);
|
||||
|
||||
list_for_each_entry(table, &gpio_lookup_list, list) {
|
||||
if (!gpiod_match_lookup_table(dev, table))
|
||||
continue;
|
||||
|
||||
desc = gpio_desc_table_match(dev, con_id, idx, flags, table);
|
||||
if (!desc)
|
||||
continue;
|
||||
|
||||
/* On IS_ERR() or match. */
|
||||
return desc;
|
||||
}
|
||||
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
static int platform_gpio_count(struct device *dev, const char *con_id)
|
||||
|
|
@ -4610,14 +4629,16 @@ static int platform_gpio_count(struct device *dev, const char *con_id)
|
|||
unsigned int count = 0;
|
||||
|
||||
scoped_guard(mutex, &gpio_lookup_lock) {
|
||||
table = gpiod_find_lookup_table(dev);
|
||||
if (!table)
|
||||
return -ENOENT;
|
||||
list_for_each_entry(table, &gpio_lookup_list, list) {
|
||||
if (!gpiod_match_lookup_table(dev, table))
|
||||
continue;
|
||||
|
||||
for (p = &table->table[0]; p->key; p++) {
|
||||
if ((con_id && p->con_id && !strcmp(con_id, p->con_id)) ||
|
||||
(!con_id && !p->con_id))
|
||||
count++;
|
||||
for (p = &table->table[0]; p->key; p++) {
|
||||
if ((con_id && p->con_id &&
|
||||
!strcmp(con_id, p->con_id)) ||
|
||||
(!con_id && !p->con_id))
|
||||
count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4696,7 +4717,8 @@ struct gpio_desc *gpiod_find_and_request(struct device *consumer,
|
|||
* lookup table for the proxy device as previously
|
||||
* we only knew the consumer's fwnode.
|
||||
*/
|
||||
ret = gpio_shared_add_proxy_lookup(consumer, lookupflags);
|
||||
ret = gpio_shared_add_proxy_lookup(consumer, con_id,
|
||||
lookupflags);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
|
|||
|
|
@ -3445,11 +3445,10 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
|
|||
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
|
||||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
|
||||
continue;
|
||||
/* skip CG for VCE/UVD/VPE, it's handled specially */
|
||||
/* skip CG for VCE/UVD, it's handled specially */
|
||||
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
|
||||
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
|
||||
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
|
||||
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VPE &&
|
||||
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
|
||||
adev->ip_blocks[i].version->funcs->set_powergating_state) {
|
||||
/* enable powergating to save power */
|
||||
|
|
@ -5867,6 +5866,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
|
|||
if (ret)
|
||||
goto mode1_reset_failed;
|
||||
|
||||
/* enable mmio access after mode 1 reset completed */
|
||||
adev->no_hw_access = false;
|
||||
|
||||
amdgpu_device_load_pci_state(adev->pdev);
|
||||
ret = amdgpu_psp_wait_for_bootloader(adev);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -89,6 +89,16 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
|
|||
return seq;
|
||||
}
|
||||
|
||||
static void amdgpu_fence_save_fence_wptr_start(struct amdgpu_fence *af)
|
||||
{
|
||||
af->fence_wptr_start = af->ring->wptr;
|
||||
}
|
||||
|
||||
static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af)
|
||||
{
|
||||
af->fence_wptr_end = af->ring->wptr;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_fence_emit - emit a fence on the requested ring
|
||||
*
|
||||
|
|
@ -116,8 +126,10 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
|
|||
&ring->fence_drv.lock,
|
||||
adev->fence_context + ring->idx, seq);
|
||||
|
||||
amdgpu_fence_save_fence_wptr_start(af);
|
||||
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
|
||||
seq, flags | AMDGPU_FENCE_FLAG_INT);
|
||||
amdgpu_fence_save_fence_wptr_end(af);
|
||||
amdgpu_fence_save_wptr(af);
|
||||
pm_runtime_get_noresume(adev_to_drm(adev)->dev);
|
||||
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
|
||||
|
|
@ -709,6 +721,7 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
|
|||
struct amdgpu_ring *ring = af->ring;
|
||||
unsigned long flags;
|
||||
u32 seq, last_seq;
|
||||
bool reemitted = false;
|
||||
|
||||
last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask;
|
||||
seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask;
|
||||
|
|
@ -726,7 +739,9 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
|
|||
if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) {
|
||||
fence = container_of(unprocessed, struct amdgpu_fence, base);
|
||||
|
||||
if (fence == af)
|
||||
if (fence->reemitted > 1)
|
||||
reemitted = true;
|
||||
else if (fence == af)
|
||||
dma_fence_set_error(&fence->base, -ETIME);
|
||||
else if (fence->context == af->context)
|
||||
dma_fence_set_error(&fence->base, -ECANCELED);
|
||||
|
|
@ -734,9 +749,12 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
|
|||
rcu_read_unlock();
|
||||
} while (last_seq != seq);
|
||||
spin_unlock_irqrestore(&ring->fence_drv.lock, flags);
|
||||
/* signal the guilty fence */
|
||||
amdgpu_fence_write(ring, (u32)af->base.seqno);
|
||||
amdgpu_fence_process(ring);
|
||||
|
||||
if (reemitted) {
|
||||
/* if we've already reemitted once then just cancel everything */
|
||||
amdgpu_fence_driver_force_completion(af->ring);
|
||||
af->ring->ring_backup_entries_to_copy = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void amdgpu_fence_save_wptr(struct amdgpu_fence *af)
|
||||
|
|
@ -784,10 +802,18 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
|
|||
/* save everything if the ring is not guilty, otherwise
|
||||
* just save the content from other contexts.
|
||||
*/
|
||||
if (!guilty_fence || (fence->context != guilty_fence->context))
|
||||
if (!fence->reemitted &&
|
||||
(!guilty_fence || (fence->context != guilty_fence->context))) {
|
||||
amdgpu_ring_backup_unprocessed_command(ring, wptr,
|
||||
fence->wptr);
|
||||
} else if (!fence->reemitted) {
|
||||
/* always save the fence */
|
||||
amdgpu_ring_backup_unprocessed_command(ring,
|
||||
fence->fence_wptr_start,
|
||||
fence->fence_wptr_end);
|
||||
}
|
||||
wptr = fence->wptr;
|
||||
fence->reemitted++;
|
||||
}
|
||||
rcu_read_unlock();
|
||||
} while (last_seq != seq);
|
||||
|
|
|
|||
|
|
@ -318,12 +318,36 @@ void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr)
|
|||
}
|
||||
EXPORT_SYMBOL(isp_kernel_buffer_free);
|
||||
|
||||
static int isp_resume(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
struct amdgpu_isp *isp = &adev->isp;
|
||||
|
||||
if (isp->funcs->hw_resume)
|
||||
return isp->funcs->hw_resume(isp);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int isp_suspend(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
struct amdgpu_isp *isp = &adev->isp;
|
||||
|
||||
if (isp->funcs->hw_suspend)
|
||||
return isp->funcs->hw_suspend(isp);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static const struct amd_ip_funcs isp_ip_funcs = {
|
||||
.name = "isp_ip",
|
||||
.early_init = isp_early_init,
|
||||
.hw_init = isp_hw_init,
|
||||
.hw_fini = isp_hw_fini,
|
||||
.is_idle = isp_is_idle,
|
||||
.suspend = isp_suspend,
|
||||
.resume = isp_resume,
|
||||
.set_clockgating_state = isp_set_clockgating_state,
|
||||
.set_powergating_state = isp_set_powergating_state,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,6 +38,8 @@ struct amdgpu_isp;
|
|||
struct isp_funcs {
|
||||
int (*hw_init)(struct amdgpu_isp *isp);
|
||||
int (*hw_fini)(struct amdgpu_isp *isp);
|
||||
int (*hw_suspend)(struct amdgpu_isp *isp);
|
||||
int (*hw_resume)(struct amdgpu_isp *isp);
|
||||
};
|
||||
|
||||
struct amdgpu_isp {
|
||||
|
|
|
|||
|
|
@ -201,6 +201,9 @@ static enum amd_ip_block_type
|
|||
type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
|
||||
AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
|
||||
break;
|
||||
case AMDGPU_HW_IP_VPE:
|
||||
type = AMD_IP_BLOCK_TYPE_VPE;
|
||||
break;
|
||||
default:
|
||||
type = AMD_IP_BLOCK_TYPE_NUM;
|
||||
break;
|
||||
|
|
@ -721,6 +724,9 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|||
case AMD_IP_BLOCK_TYPE_UVD:
|
||||
count = adev->uvd.num_uvd_inst;
|
||||
break;
|
||||
case AMD_IP_BLOCK_TYPE_VPE:
|
||||
count = adev->vpe.num_instances;
|
||||
break;
|
||||
/* For all other IP block types not listed in the switch statement
|
||||
* the ip status is valid here and the instance count is one.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -144,10 +144,15 @@ struct amdgpu_fence {
|
|||
struct amdgpu_ring *ring;
|
||||
ktime_t start_timestamp;
|
||||
|
||||
/* wptr for the fence for resets */
|
||||
/* wptr for the total submission for resets */
|
||||
u64 wptr;
|
||||
/* fence context for resets */
|
||||
u64 context;
|
||||
/* has this fence been reemitted */
|
||||
unsigned int reemitted;
|
||||
/* wptr for the fence for the submission */
|
||||
u64 fence_wptr_start;
|
||||
u64 fence_wptr_end;
|
||||
};
|
||||
|
||||
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include "amdgpu.h"
|
||||
#include "isp_v4_1_1.h"
|
||||
|
||||
|
|
@ -145,6 +146,9 @@ static int isp_genpd_add_device(struct device *dev, void *data)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* The devices will be managed by the pm ops from the parent */
|
||||
dev_pm_syscore_device(dev, true);
|
||||
|
||||
exit:
|
||||
/* Continue to add */
|
||||
return 0;
|
||||
|
|
@ -177,12 +181,47 @@ static int isp_genpd_remove_device(struct device *dev, void *data)
|
|||
drm_err(&adev->ddev, "Failed to remove dev from genpd %d\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
dev_pm_syscore_device(dev, false);
|
||||
|
||||
exit:
|
||||
/* Continue to remove */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int isp_suspend_device(struct device *dev, void *data)
|
||||
{
|
||||
return pm_runtime_force_suspend(dev);
|
||||
}
|
||||
|
||||
static int isp_resume_device(struct device *dev, void *data)
|
||||
{
|
||||
return pm_runtime_force_resume(dev);
|
||||
}
|
||||
|
||||
static int isp_v4_1_1_hw_suspend(struct amdgpu_isp *isp)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = device_for_each_child(isp->parent, NULL,
|
||||
isp_suspend_device);
|
||||
if (r)
|
||||
dev_err(isp->parent, "failed to suspend hw devices (%d)\n", r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int isp_v4_1_1_hw_resume(struct amdgpu_isp *isp)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = device_for_each_child(isp->parent, NULL,
|
||||
isp_resume_device);
|
||||
if (r)
|
||||
dev_err(isp->parent, "failed to resume hw device (%d)\n", r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
|
||||
{
|
||||
const struct software_node *amd_camera_node, *isp4_node;
|
||||
|
|
@ -369,6 +408,8 @@ static int isp_v4_1_1_hw_fini(struct amdgpu_isp *isp)
|
|||
static const struct isp_funcs isp_v4_1_1_funcs = {
|
||||
.hw_init = isp_v4_1_1_hw_init,
|
||||
.hw_fini = isp_v4_1_1_hw_fini,
|
||||
.hw_suspend = isp_v4_1_1_hw_suspend,
|
||||
.hw_resume = isp_v4_1_1_hw_resume,
|
||||
};
|
||||
|
||||
void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp)
|
||||
|
|
|
|||
|
|
@ -763,14 +763,14 @@ static enum bp_result bios_parser_encoder_control(
|
|||
return BP_RESULT_FAILURE;
|
||||
|
||||
return bp->cmd_tbl.dac1_encoder_control(
|
||||
bp, cntl->action == ENCODER_CONTROL_ENABLE,
|
||||
bp, cntl->action,
|
||||
cntl->pixel_clock, ATOM_DAC1_PS2);
|
||||
} else if (cntl->engine_id == ENGINE_ID_DACB) {
|
||||
if (!bp->cmd_tbl.dac2_encoder_control)
|
||||
return BP_RESULT_FAILURE;
|
||||
|
||||
return bp->cmd_tbl.dac2_encoder_control(
|
||||
bp, cntl->action == ENCODER_CONTROL_ENABLE,
|
||||
bp, cntl->action,
|
||||
cntl->pixel_clock, ATOM_DAC1_PS2);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1797,7 +1797,30 @@ static enum bp_result select_crtc_source_v3(
|
|||
¶ms.ucEncodeMode))
|
||||
return BP_RESULT_BADINPUT;
|
||||
|
||||
params.ucDstBpc = bp_params->bit_depth;
|
||||
switch (bp_params->color_depth) {
|
||||
case COLOR_DEPTH_UNDEFINED:
|
||||
params.ucDstBpc = PANEL_BPC_UNDEFINE;
|
||||
break;
|
||||
case COLOR_DEPTH_666:
|
||||
params.ucDstBpc = PANEL_6BIT_PER_COLOR;
|
||||
break;
|
||||
default:
|
||||
case COLOR_DEPTH_888:
|
||||
params.ucDstBpc = PANEL_8BIT_PER_COLOR;
|
||||
break;
|
||||
case COLOR_DEPTH_101010:
|
||||
params.ucDstBpc = PANEL_10BIT_PER_COLOR;
|
||||
break;
|
||||
case COLOR_DEPTH_121212:
|
||||
params.ucDstBpc = PANEL_12BIT_PER_COLOR;
|
||||
break;
|
||||
case COLOR_DEPTH_141414:
|
||||
dm_error("14-bit color not supported by SelectCRTC_Source v3\n");
|
||||
break;
|
||||
case COLOR_DEPTH_161616:
|
||||
params.ucDstBpc = PANEL_16BIT_PER_COLOR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
|
||||
result = BP_RESULT_OK;
|
||||
|
|
@ -1815,12 +1838,12 @@ static enum bp_result select_crtc_source_v3(
|
|||
|
||||
static enum bp_result dac1_encoder_control_v1(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard);
|
||||
static enum bp_result dac2_encoder_control_v1(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard);
|
||||
|
||||
|
|
@ -1846,12 +1869,15 @@ static void init_dac_encoder_control(struct bios_parser *bp)
|
|||
|
||||
static void dac_encoder_control_prepare_params(
|
||||
DAC_ENCODER_CONTROL_PS_ALLOCATION *params,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard)
|
||||
{
|
||||
params->ucDacStandard = dac_standard;
|
||||
if (enable)
|
||||
if (action == ENCODER_CONTROL_SETUP ||
|
||||
action == ENCODER_CONTROL_INIT)
|
||||
params->ucAction = ATOM_ENCODER_INIT;
|
||||
else if (action == ENCODER_CONTROL_ENABLE)
|
||||
params->ucAction = ATOM_ENABLE;
|
||||
else
|
||||
params->ucAction = ATOM_DISABLE;
|
||||
|
|
@ -1864,7 +1890,7 @@ static void dac_encoder_control_prepare_params(
|
|||
|
||||
static enum bp_result dac1_encoder_control_v1(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard)
|
||||
{
|
||||
|
|
@ -1873,7 +1899,7 @@ static enum bp_result dac1_encoder_control_v1(
|
|||
|
||||
dac_encoder_control_prepare_params(
|
||||
¶ms,
|
||||
enable,
|
||||
action,
|
||||
pixel_clock,
|
||||
dac_standard);
|
||||
|
||||
|
|
@ -1885,7 +1911,7 @@ static enum bp_result dac1_encoder_control_v1(
|
|||
|
||||
static enum bp_result dac2_encoder_control_v1(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard)
|
||||
{
|
||||
|
|
@ -1894,7 +1920,7 @@ static enum bp_result dac2_encoder_control_v1(
|
|||
|
||||
dac_encoder_control_prepare_params(
|
||||
¶ms,
|
||||
enable,
|
||||
action,
|
||||
pixel_clock,
|
||||
dac_standard);
|
||||
|
||||
|
|
|
|||
|
|
@ -57,12 +57,12 @@ struct cmd_tbl {
|
|||
struct bp_crtc_source_select *bp_params);
|
||||
enum bp_result (*dac1_encoder_control)(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard);
|
||||
enum bp_result (*dac2_encoder_control)(
|
||||
struct bios_parser *bp,
|
||||
bool enable,
|
||||
enum bp_encoder_control_action action,
|
||||
uint32_t pixel_clock,
|
||||
uint8_t dac_standard);
|
||||
enum bp_result (*dac1_output_control)(
|
||||
|
|
|
|||
|
|
@ -30,7 +30,11 @@ dml_rcflags := $(CC_FLAGS_NO_FPU)
|
|||
|
||||
ifneq ($(CONFIG_FRAME_WARN),0)
|
||||
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
|
||||
frame_warn_limit := 3072
|
||||
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
|
||||
frame_warn_limit := 4096
|
||||
else
|
||||
frame_warn_limit := 3072
|
||||
endif
|
||||
else
|
||||
frame_warn_limit := 2048
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -77,32 +77,14 @@ static unsigned int dscceComputeDelay(
|
|||
static unsigned int dscComputeDelay(
|
||||
enum output_format_class pixelFormat,
|
||||
enum output_encoder_class Output);
|
||||
// Super monster function with some 45 argument
|
||||
static bool CalculatePrefetchSchedule(
|
||||
struct display_mode_lib *mode_lib,
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
|
||||
unsigned int k,
|
||||
Pipe *myPipe,
|
||||
unsigned int DSCDelay,
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater,
|
||||
double DPPCLKDelaySCL,
|
||||
double DPPCLKDelaySCLLBOnly,
|
||||
double DPPCLKDelayCNVCCursor,
|
||||
double DISPCLKDelaySubtotal,
|
||||
unsigned int DPP_RECOUT_WIDTH,
|
||||
enum output_format_class OutputFormat,
|
||||
unsigned int MaxInterDCNTileRepeaters,
|
||||
unsigned int VStartup,
|
||||
unsigned int MaxVStartup,
|
||||
unsigned int GPUVMPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
double HostVMMinPageSize,
|
||||
bool DynamicMetadataEnable,
|
||||
bool DynamicMetadataVMEnabled,
|
||||
int DynamicMetadataLinesBeforeActiveRequired,
|
||||
unsigned int DynamicMetadataTransmittedBytes,
|
||||
double UrgentLatency,
|
||||
double UrgentExtraLatency,
|
||||
double TCalc,
|
||||
|
|
@ -116,7 +98,6 @@ static bool CalculatePrefetchSchedule(
|
|||
unsigned int MaxNumSwathY,
|
||||
double PrefetchSourceLinesC,
|
||||
unsigned int SwathWidthC,
|
||||
int BytePerPixelC,
|
||||
double VInitPreFillC,
|
||||
unsigned int MaxNumSwathC,
|
||||
long swath_width_luma_ub,
|
||||
|
|
@ -124,9 +105,6 @@ static bool CalculatePrefetchSchedule(
|
|||
unsigned int SwathHeightY,
|
||||
unsigned int SwathHeightC,
|
||||
double TWait,
|
||||
bool ProgressiveToInterlaceUnitInOPP,
|
||||
double *DSTXAfterScaler,
|
||||
double *DSTYAfterScaler,
|
||||
double *DestinationLinesForPrefetch,
|
||||
double *PrefetchBandwidth,
|
||||
double *DestinationLinesToRequestVMInVBlank,
|
||||
|
|
@ -135,14 +113,7 @@ static bool CalculatePrefetchSchedule(
|
|||
double *VRatioPrefetchC,
|
||||
double *RequiredPrefetchPixDataBWLuma,
|
||||
double *RequiredPrefetchPixDataBWChroma,
|
||||
bool *NotEnoughTimeForDynamicMetadata,
|
||||
double *Tno_bw,
|
||||
double *prefetch_vmrow_bw,
|
||||
double *Tdmdl_vm,
|
||||
double *Tdmdl,
|
||||
unsigned int *VUpdateOffsetPix,
|
||||
double *VUpdateWidthPix,
|
||||
double *VReadyOffsetPix);
|
||||
bool *NotEnoughTimeForDynamicMetadata);
|
||||
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
|
||||
static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
|
||||
static void CalculateDCCConfiguration(
|
||||
|
|
@ -294,62 +265,23 @@ static void CalculateDynamicMetadataParameters(
|
|||
static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActivePlanes,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int DPPOutputBufferPixels,
|
||||
unsigned int DETBufferSizeInKByte,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool GPUVMEnable,
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int MetaChunkSize,
|
||||
double UrgentLatency,
|
||||
double ExtraLatency,
|
||||
double WritebackLatency,
|
||||
double WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DRAMClockChangeLatency,
|
||||
double SRExitTime,
|
||||
double SREnterPlusExitTime,
|
||||
double DCFCLKDeepSleep,
|
||||
unsigned int DPPPerPlane[],
|
||||
bool DCCEnable[],
|
||||
double DPPCLK[],
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int vtaps[],
|
||||
unsigned int VTAPsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double *UrgentWatermark,
|
||||
double *WritebackUrgentWatermark,
|
||||
double *DRAMClockChangeWatermark,
|
||||
double *WritebackDRAMClockChangeWatermark,
|
||||
double *StutterExitWatermark,
|
||||
double *StutterEnterPlusExitWatermark,
|
||||
double *MinActiveDRAMClockChangeLatencySupported);
|
||||
enum clock_change_support *DRAMClockChangeSupport);
|
||||
static void CalculateDCFCLKDeepSleep(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int NumberOfActivePlanes,
|
||||
|
|
@ -810,29 +742,12 @@ static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum o
|
|||
|
||||
static bool CalculatePrefetchSchedule(
|
||||
struct display_mode_lib *mode_lib,
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
|
||||
unsigned int k,
|
||||
Pipe *myPipe,
|
||||
unsigned int DSCDelay,
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater,
|
||||
double DPPCLKDelaySCL,
|
||||
double DPPCLKDelaySCLLBOnly,
|
||||
double DPPCLKDelayCNVCCursor,
|
||||
double DISPCLKDelaySubtotal,
|
||||
unsigned int DPP_RECOUT_WIDTH,
|
||||
enum output_format_class OutputFormat,
|
||||
unsigned int MaxInterDCNTileRepeaters,
|
||||
unsigned int VStartup,
|
||||
unsigned int MaxVStartup,
|
||||
unsigned int GPUVMPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
double HostVMMinPageSize,
|
||||
bool DynamicMetadataEnable,
|
||||
bool DynamicMetadataVMEnabled,
|
||||
int DynamicMetadataLinesBeforeActiveRequired,
|
||||
unsigned int DynamicMetadataTransmittedBytes,
|
||||
double UrgentLatency,
|
||||
double UrgentExtraLatency,
|
||||
double TCalc,
|
||||
|
|
@ -846,7 +761,6 @@ static bool CalculatePrefetchSchedule(
|
|||
unsigned int MaxNumSwathY,
|
||||
double PrefetchSourceLinesC,
|
||||
unsigned int SwathWidthC,
|
||||
int BytePerPixelC,
|
||||
double VInitPreFillC,
|
||||
unsigned int MaxNumSwathC,
|
||||
long swath_width_luma_ub,
|
||||
|
|
@ -854,9 +768,6 @@ static bool CalculatePrefetchSchedule(
|
|||
unsigned int SwathHeightY,
|
||||
unsigned int SwathHeightC,
|
||||
double TWait,
|
||||
bool ProgressiveToInterlaceUnitInOPP,
|
||||
double *DSTXAfterScaler,
|
||||
double *DSTYAfterScaler,
|
||||
double *DestinationLinesForPrefetch,
|
||||
double *PrefetchBandwidth,
|
||||
double *DestinationLinesToRequestVMInVBlank,
|
||||
|
|
@ -865,15 +776,10 @@ static bool CalculatePrefetchSchedule(
|
|||
double *VRatioPrefetchC,
|
||||
double *RequiredPrefetchPixDataBWLuma,
|
||||
double *RequiredPrefetchPixDataBWChroma,
|
||||
bool *NotEnoughTimeForDynamicMetadata,
|
||||
double *Tno_bw,
|
||||
double *prefetch_vmrow_bw,
|
||||
double *Tdmdl_vm,
|
||||
double *Tdmdl,
|
||||
unsigned int *VUpdateOffsetPix,
|
||||
double *VUpdateWidthPix,
|
||||
double *VReadyOffsetPix)
|
||||
bool *NotEnoughTimeForDynamicMetadata)
|
||||
{
|
||||
struct vba_vars_st *v = &mode_lib->vba;
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
|
||||
bool MyError = false;
|
||||
unsigned int DPPCycles = 0, DISPCLKCycles = 0;
|
||||
double DSTTotalPixelsAfterScaler = 0;
|
||||
|
|
@ -905,26 +811,26 @@ static bool CalculatePrefetchSchedule(
|
|||
double Tdmec = 0;
|
||||
double Tdmsks = 0;
|
||||
|
||||
if (GPUVMEnable == true && HostVMEnable == true) {
|
||||
HostVMInefficiencyFactor = PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
|
||||
HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
|
||||
if (v->GPUVMEnable == true && v->HostVMEnable == true) {
|
||||
HostVMInefficiencyFactor = v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
|
||||
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
|
||||
} else {
|
||||
HostVMInefficiencyFactor = 1;
|
||||
HostVMDynamicLevelsTrips = 0;
|
||||
}
|
||||
|
||||
CalculateDynamicMetadataParameters(
|
||||
MaxInterDCNTileRepeaters,
|
||||
v->MaxInterDCNTileRepeaters,
|
||||
myPipe->DPPCLK,
|
||||
myPipe->DISPCLK,
|
||||
myPipe->DCFCLKDeepSleep,
|
||||
myPipe->PixelClock,
|
||||
myPipe->HTotal,
|
||||
myPipe->VBlank,
|
||||
DynamicMetadataTransmittedBytes,
|
||||
DynamicMetadataLinesBeforeActiveRequired,
|
||||
v->DynamicMetadataTransmittedBytes[k],
|
||||
v->DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
myPipe->InterlaceEnable,
|
||||
ProgressiveToInterlaceUnitInOPP,
|
||||
v->ProgressiveToInterlaceUnitInOPP,
|
||||
&Tsetup,
|
||||
&Tdmbf,
|
||||
&Tdmec,
|
||||
|
|
@ -932,16 +838,16 @@ static bool CalculatePrefetchSchedule(
|
|||
|
||||
LineTime = myPipe->HTotal / myPipe->PixelClock;
|
||||
trip_to_mem = UrgentLatency;
|
||||
Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
|
||||
if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) {
|
||||
*Tdmdl = TWait + Tvm_trips + trip_to_mem;
|
||||
if (v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true) {
|
||||
v->Tdmdl[k] = TWait + Tvm_trips + trip_to_mem;
|
||||
} else {
|
||||
*Tdmdl = TWait + UrgentExtraLatency;
|
||||
v->Tdmdl[k] = TWait + UrgentExtraLatency;
|
||||
}
|
||||
|
||||
if (DynamicMetadataEnable == true) {
|
||||
if (VStartup * LineTime < Tsetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
|
||||
if (v->DynamicMetadataEnable[k] == true) {
|
||||
if (VStartup * LineTime < Tsetup + v->Tdmdl[k] + Tdmbf + Tdmec + Tdmsks) {
|
||||
*NotEnoughTimeForDynamicMetadata = true;
|
||||
} else {
|
||||
*NotEnoughTimeForDynamicMetadata = false;
|
||||
|
|
@ -949,39 +855,39 @@ static bool CalculatePrefetchSchedule(
|
|||
dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
|
||||
dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
|
||||
dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
|
||||
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl);
|
||||
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
|
||||
}
|
||||
} else {
|
||||
*NotEnoughTimeForDynamicMetadata = false;
|
||||
}
|
||||
|
||||
*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0);
|
||||
v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
|
||||
|
||||
if (myPipe->ScalerEnabled)
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL;
|
||||
else
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly;
|
||||
|
||||
DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
|
||||
DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor;
|
||||
|
||||
DISPCLKCycles = DISPCLKDelaySubtotal;
|
||||
DISPCLKCycles = v->DISPCLKDelaySubtotal;
|
||||
|
||||
if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
|
||||
return true;
|
||||
|
||||
*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
|
||||
v->DSTXAfterScaler[k] = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
|
||||
+ DSCDelay;
|
||||
|
||||
*DSTXAfterScaler = *DSTXAfterScaler + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
|
||||
v->DSTXAfterScaler[k] = v->DSTXAfterScaler[k] + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
|
||||
|
||||
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
|
||||
*DSTYAfterScaler = 1;
|
||||
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
|
||||
v->DSTYAfterScaler[k] = 1;
|
||||
else
|
||||
*DSTYAfterScaler = 0;
|
||||
v->DSTYAfterScaler[k] = 0;
|
||||
|
||||
DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler;
|
||||
*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
|
||||
*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
|
||||
DSTTotalPixelsAfterScaler = v->DSTYAfterScaler[k] * myPipe->HTotal + v->DSTXAfterScaler[k];
|
||||
v->DSTYAfterScaler[k] = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
|
||||
v->DSTXAfterScaler[k] = DSTTotalPixelsAfterScaler - ((double) (v->DSTYAfterScaler[k] * myPipe->HTotal));
|
||||
|
||||
MyError = false;
|
||||
|
||||
|
|
@ -990,33 +896,33 @@ static bool CalculatePrefetchSchedule(
|
|||
Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
|
||||
Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
|
||||
|
||||
if (GPUVMEnable) {
|
||||
if (GPUVMPageTableLevels >= 3) {
|
||||
*Tno_bw = UrgentExtraLatency + trip_to_mem * ((GPUVMPageTableLevels - 2) - 1);
|
||||
if (v->GPUVMEnable) {
|
||||
if (v->GPUVMMaxPageTableLevels >= 3) {
|
||||
v->Tno_bw[k] = UrgentExtraLatency + trip_to_mem * ((v->GPUVMMaxPageTableLevels - 2) - 1);
|
||||
} else
|
||||
*Tno_bw = 0;
|
||||
v->Tno_bw[k] = 0;
|
||||
} else if (!myPipe->DCCEnable)
|
||||
*Tno_bw = LineTime;
|
||||
v->Tno_bw[k] = LineTime;
|
||||
else
|
||||
*Tno_bw = LineTime / 4;
|
||||
v->Tno_bw[k] = LineTime / 4;
|
||||
|
||||
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime
|
||||
- (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
|
||||
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
|
||||
- (v->DSTYAfterScaler[k] + v->DSTXAfterScaler[k] / myPipe->HTotal);
|
||||
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
|
||||
|
||||
Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC);
|
||||
Tsw_oto = Lsw_oto * LineTime;
|
||||
|
||||
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC) / Tsw_oto;
|
||||
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k]) / Tsw_oto;
|
||||
|
||||
if (GPUVMEnable == true) {
|
||||
Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
|
||||
if (v->GPUVMEnable == true) {
|
||||
Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
|
||||
Tvm_trips,
|
||||
LineTime / 4.0);
|
||||
} else
|
||||
Tvm_oto = LineTime / 4.0;
|
||||
|
||||
if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
Tr0_oto = dml_max3(
|
||||
(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
|
||||
LineTime - Tvm_oto, LineTime / 4);
|
||||
|
|
@ -1042,10 +948,10 @@ static bool CalculatePrefetchSchedule(
|
|||
dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
|
||||
dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
|
||||
dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
|
||||
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", *Tdmdl_vm);
|
||||
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl);
|
||||
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", *DSTXAfterScaler);
|
||||
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)*DSTYAfterScaler);
|
||||
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", v->Tdmdl_vm[k]);
|
||||
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
|
||||
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", v->DSTXAfterScaler[k]);
|
||||
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)v->DSTYAfterScaler[k]);
|
||||
|
||||
*PrefetchBandwidth = 0;
|
||||
*DestinationLinesToRequestVMInVBlank = 0;
|
||||
|
|
@ -1059,26 +965,26 @@ static bool CalculatePrefetchSchedule(
|
|||
double PrefetchBandwidth3 = 0;
|
||||
double PrefetchBandwidth4 = 0;
|
||||
|
||||
if (Tpre_rounded - *Tno_bw > 0)
|
||||
if (Tpre_rounded - v->Tno_bw[k] > 0)
|
||||
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
|
||||
+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
|
||||
+ PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY
|
||||
+ PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC)
|
||||
/ (Tpre_rounded - *Tno_bw);
|
||||
+ PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
|
||||
/ (Tpre_rounded - v->Tno_bw[k]);
|
||||
else
|
||||
PrefetchBandwidth1 = 0;
|
||||
|
||||
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - *Tno_bw) > 0) {
|
||||
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - *Tno_bw);
|
||||
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]) > 0) {
|
||||
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]);
|
||||
}
|
||||
|
||||
if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0)
|
||||
if (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded > 0)
|
||||
PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame *
|
||||
HostVMInefficiencyFactor + PrefetchSourceLinesY *
|
||||
swath_width_luma_ub * BytePerPixelY +
|
||||
PrefetchSourceLinesC * swath_width_chroma_ub *
|
||||
BytePerPixelC) /
|
||||
(Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded);
|
||||
v->BytePerPixelC[k]) /
|
||||
(Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded);
|
||||
else
|
||||
PrefetchBandwidth2 = 0;
|
||||
|
||||
|
|
@ -1086,7 +992,7 @@ static bool CalculatePrefetchSchedule(
|
|||
PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow *
|
||||
HostVMInefficiencyFactor + PrefetchSourceLinesY *
|
||||
swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC *
|
||||
swath_width_chroma_ub * BytePerPixelC) / (Tpre_rounded -
|
||||
swath_width_chroma_ub * v->BytePerPixelC[k]) / (Tpre_rounded -
|
||||
Tvm_trips_rounded);
|
||||
else
|
||||
PrefetchBandwidth3 = 0;
|
||||
|
|
@ -1096,7 +1002,7 @@ static bool CalculatePrefetchSchedule(
|
|||
}
|
||||
|
||||
if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0)
|
||||
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC)
|
||||
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
|
||||
/ (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
|
||||
else
|
||||
PrefetchBandwidth4 = 0;
|
||||
|
|
@ -1107,7 +1013,7 @@ static bool CalculatePrefetchSchedule(
|
|||
bool Case3OK;
|
||||
|
||||
if (PrefetchBandwidth1 > 0) {
|
||||
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
|
||||
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
|
||||
>= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) {
|
||||
Case1OK = true;
|
||||
} else {
|
||||
|
|
@ -1118,7 +1024,7 @@ static bool CalculatePrefetchSchedule(
|
|||
}
|
||||
|
||||
if (PrefetchBandwidth2 > 0) {
|
||||
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
|
||||
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
|
||||
>= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) {
|
||||
Case2OK = true;
|
||||
} else {
|
||||
|
|
@ -1129,7 +1035,7 @@ static bool CalculatePrefetchSchedule(
|
|||
}
|
||||
|
||||
if (PrefetchBandwidth3 > 0) {
|
||||
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
|
||||
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
|
||||
< Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) {
|
||||
Case3OK = true;
|
||||
} else {
|
||||
|
|
@ -1152,13 +1058,13 @@ static bool CalculatePrefetchSchedule(
|
|||
dml_print("DML: prefetch_bw_equ: %f\n", prefetch_bw_equ);
|
||||
|
||||
if (prefetch_bw_equ > 0) {
|
||||
if (GPUVMEnable) {
|
||||
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
|
||||
if (v->GPUVMEnable) {
|
||||
Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
|
||||
} else {
|
||||
Tvm_equ = LineTime / 4;
|
||||
}
|
||||
|
||||
if ((GPUVMEnable || myPipe->DCCEnable)) {
|
||||
if ((v->GPUVMEnable || myPipe->DCCEnable)) {
|
||||
Tr0_equ = dml_max4(
|
||||
(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ,
|
||||
Tr0_trips,
|
||||
|
|
@ -1227,7 +1133,7 @@ static bool CalculatePrefetchSchedule(
|
|||
}
|
||||
|
||||
*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * BytePerPixelY * swath_width_luma_ub / LineTime;
|
||||
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * BytePerPixelC * swath_width_chroma_ub / LineTime;
|
||||
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * v->BytePerPixelC[k] * swath_width_chroma_ub / LineTime;
|
||||
} else {
|
||||
MyError = true;
|
||||
dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
|
||||
|
|
@ -1243,9 +1149,9 @@ static bool CalculatePrefetchSchedule(
|
|||
dml_print("DML: Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
|
||||
dml_print("DML: Tr1: %fus - time to fetch second row of data pagetables and second row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
|
||||
dml_print("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", (double)LinesToRequestPrefetchPixelData * LineTime);
|
||||
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (*DSTYAfterScaler + ((*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime);
|
||||
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime);
|
||||
dml_print("DML: Tvstartup - Tsetup - Tcalc - Twait - Tpre - To > 0\n");
|
||||
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (*DSTYAfterScaler + ((*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
|
||||
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
|
||||
dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
|
||||
|
||||
} else {
|
||||
|
|
@ -1276,7 +1182,7 @@ static bool CalculatePrefetchSchedule(
|
|||
dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
|
||||
}
|
||||
|
||||
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
|
||||
v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
|
||||
}
|
||||
|
||||
if (MyError) {
|
||||
|
|
@ -2437,30 +2343,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
|
||||
v->ErrorResult[k] = CalculatePrefetchSchedule(
|
||||
mode_lib,
|
||||
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
|
||||
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
|
||||
k,
|
||||
&myPipe,
|
||||
v->DSCDelay[k],
|
||||
v->DPPCLKDelaySubtotal
|
||||
+ v->DPPCLKDelayCNVCFormater,
|
||||
v->DPPCLKDelaySCL,
|
||||
v->DPPCLKDelaySCLLBOnly,
|
||||
v->DPPCLKDelayCNVCCursor,
|
||||
v->DISPCLKDelaySubtotal,
|
||||
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
|
||||
v->OutputFormat[k],
|
||||
v->MaxInterDCNTileRepeaters,
|
||||
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
|
||||
v->MaxVStartupLines[k],
|
||||
v->GPUVMMaxPageTableLevels,
|
||||
v->GPUVMEnable,
|
||||
v->HostVMEnable,
|
||||
v->HostVMMaxNonCachedPageTableLevels,
|
||||
v->HostVMMinPageSize,
|
||||
v->DynamicMetadataEnable[k],
|
||||
v->DynamicMetadataVMEnabled,
|
||||
v->DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
v->DynamicMetadataTransmittedBytes[k],
|
||||
v->UrgentLatency,
|
||||
v->UrgentExtraLatency,
|
||||
v->TCalc,
|
||||
|
|
@ -2474,7 +2362,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
v->MaxNumSwathY[k],
|
||||
v->PrefetchSourceLinesC[k],
|
||||
v->SwathWidthC[k],
|
||||
v->BytePerPixelC[k],
|
||||
v->VInitPreFillC[k],
|
||||
v->MaxNumSwathC[k],
|
||||
v->swath_width_luma_ub[k],
|
||||
|
|
@ -2482,9 +2369,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
v->SwathHeightY[k],
|
||||
v->SwathHeightC[k],
|
||||
TWait,
|
||||
v->ProgressiveToInterlaceUnitInOPP,
|
||||
&v->DSTXAfterScaler[k],
|
||||
&v->DSTYAfterScaler[k],
|
||||
&v->DestinationLinesForPrefetch[k],
|
||||
&v->PrefetchBandwidth[k],
|
||||
&v->DestinationLinesToRequestVMInVBlank[k],
|
||||
|
|
@ -2493,14 +2377,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
&v->VRatioPrefetchC[k],
|
||||
&v->RequiredPrefetchPixDataBWLuma[k],
|
||||
&v->RequiredPrefetchPixDataBWChroma[k],
|
||||
&v->NotEnoughTimeForDynamicMetadata[k],
|
||||
&v->Tno_bw[k],
|
||||
&v->prefetch_vmrow_bw[k],
|
||||
&v->Tdmdl_vm[k],
|
||||
&v->Tdmdl[k],
|
||||
&v->VUpdateOffsetPix[k],
|
||||
&v->VUpdateWidthPix[k],
|
||||
&v->VReadyOffsetPix[k]);
|
||||
&v->NotEnoughTimeForDynamicMetadata[k]);
|
||||
if (v->BlendingAndTiming[k] == k) {
|
||||
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
|
||||
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k];
|
||||
|
|
@ -2730,62 +2607,23 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
mode_lib,
|
||||
PrefetchMode,
|
||||
v->NumberOfActivePlanes,
|
||||
v->MaxLineBufferLines,
|
||||
v->LineBufferSize,
|
||||
v->DPPOutputBufferPixels,
|
||||
v->DETBufferSizeInKByte[0],
|
||||
v->WritebackInterfaceBufferSize,
|
||||
v->DCFCLK,
|
||||
v->ReturnBW,
|
||||
v->GPUVMEnable,
|
||||
v->dpte_group_bytes,
|
||||
v->MetaChunkSize,
|
||||
v->UrgentLatency,
|
||||
v->UrgentExtraLatency,
|
||||
v->WritebackLatency,
|
||||
v->WritebackChunkSize,
|
||||
v->SOCCLK,
|
||||
v->FinalDRAMClockChangeLatency,
|
||||
v->SRExitTime,
|
||||
v->SREnterPlusExitTime,
|
||||
v->DCFCLKDeepSleep,
|
||||
v->DPPPerPlane,
|
||||
v->DCCEnable,
|
||||
v->DPPCLK,
|
||||
v->DETBufferSizeY,
|
||||
v->DETBufferSizeC,
|
||||
v->SwathHeightY,
|
||||
v->SwathHeightC,
|
||||
v->LBBitPerPixel,
|
||||
v->SwathWidthY,
|
||||
v->SwathWidthC,
|
||||
v->HRatio,
|
||||
v->HRatioChroma,
|
||||
v->vtaps,
|
||||
v->VTAPsChroma,
|
||||
v->VRatio,
|
||||
v->VRatioChroma,
|
||||
v->HTotal,
|
||||
v->PixelClock,
|
||||
v->BlendingAndTiming,
|
||||
v->BytePerPixelDETY,
|
||||
v->BytePerPixelDETC,
|
||||
v->DSTXAfterScaler,
|
||||
v->DSTYAfterScaler,
|
||||
v->WritebackEnable,
|
||||
v->WritebackPixelFormat,
|
||||
v->WritebackDestinationWidth,
|
||||
v->WritebackDestinationHeight,
|
||||
v->WritebackSourceHeight,
|
||||
&DRAMClockChangeSupport,
|
||||
&v->UrgentWatermark,
|
||||
&v->WritebackUrgentWatermark,
|
||||
&v->DRAMClockChangeWatermark,
|
||||
&v->WritebackDRAMClockChangeWatermark,
|
||||
&v->StutterExitWatermark,
|
||||
&v->StutterEnterPlusExitWatermark,
|
||||
&v->MinActiveDRAMClockChangeLatencySupported);
|
||||
&DRAMClockChangeSupport);
|
||||
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
|
|
@ -4770,29 +4608,12 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
|
||||
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
|
||||
mode_lib,
|
||||
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
|
||||
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
|
||||
k,
|
||||
&myPipe,
|
||||
v->DSCDelayPerState[i][k],
|
||||
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
|
||||
v->DPPCLKDelaySCL,
|
||||
v->DPPCLKDelaySCLLBOnly,
|
||||
v->DPPCLKDelayCNVCCursor,
|
||||
v->DISPCLKDelaySubtotal,
|
||||
v->SwathWidthYThisState[k] / v->HRatio[k],
|
||||
v->OutputFormat[k],
|
||||
v->MaxInterDCNTileRepeaters,
|
||||
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
|
||||
v->MaximumVStartup[i][j][k],
|
||||
v->GPUVMMaxPageTableLevels,
|
||||
v->GPUVMEnable,
|
||||
v->HostVMEnable,
|
||||
v->HostVMMaxNonCachedPageTableLevels,
|
||||
v->HostVMMinPageSize,
|
||||
v->DynamicMetadataEnable[k],
|
||||
v->DynamicMetadataVMEnabled,
|
||||
v->DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
v->DynamicMetadataTransmittedBytes[k],
|
||||
v->UrgLatency[i],
|
||||
v->ExtraLatency,
|
||||
v->TimeCalc,
|
||||
|
|
@ -4806,7 +4627,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
v->MaxNumSwY[k],
|
||||
v->PrefetchLinesC[i][j][k],
|
||||
v->SwathWidthCThisState[k],
|
||||
v->BytePerPixelC[k],
|
||||
v->PrefillC[k],
|
||||
v->MaxNumSwC[k],
|
||||
v->swath_width_luma_ub_this_state[k],
|
||||
|
|
@ -4814,9 +4634,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
v->SwathHeightYThisState[k],
|
||||
v->SwathHeightCThisState[k],
|
||||
v->TWait,
|
||||
v->ProgressiveToInterlaceUnitInOPP,
|
||||
&v->DSTXAfterScaler[k],
|
||||
&v->DSTYAfterScaler[k],
|
||||
&v->LineTimesForPrefetch[k],
|
||||
&v->PrefetchBW[k],
|
||||
&v->LinesForMetaPTE[k],
|
||||
|
|
@ -4825,14 +4642,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
&v->VRatioPreC[i][j][k],
|
||||
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
|
||||
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
|
||||
&v->NoTimeForDynamicMetadata[i][j][k],
|
||||
&v->Tno_bw[k],
|
||||
&v->prefetch_vmrow_bw[k],
|
||||
&v->Tdmdl_vm[k],
|
||||
&v->Tdmdl[k],
|
||||
&v->VUpdateOffsetPix[k],
|
||||
&v->VUpdateWidthPix[k],
|
||||
&v->VReadyOffsetPix[k]);
|
||||
&v->NoTimeForDynamicMetadata[i][j][k]);
|
||||
}
|
||||
|
||||
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
|
||||
|
|
@ -5007,62 +4817,23 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
mode_lib,
|
||||
v->PrefetchModePerState[i][j],
|
||||
v->NumberOfActivePlanes,
|
||||
v->MaxLineBufferLines,
|
||||
v->LineBufferSize,
|
||||
v->DPPOutputBufferPixels,
|
||||
v->DETBufferSizeInKByte[0],
|
||||
v->WritebackInterfaceBufferSize,
|
||||
v->DCFCLKState[i][j],
|
||||
v->ReturnBWPerState[i][j],
|
||||
v->GPUVMEnable,
|
||||
v->dpte_group_bytes,
|
||||
v->MetaChunkSize,
|
||||
v->UrgLatency[i],
|
||||
v->ExtraLatency,
|
||||
v->WritebackLatency,
|
||||
v->WritebackChunkSize,
|
||||
v->SOCCLKPerState[i],
|
||||
v->FinalDRAMClockChangeLatency,
|
||||
v->SRExitTime,
|
||||
v->SREnterPlusExitTime,
|
||||
v->ProjectedDCFCLKDeepSleep[i][j],
|
||||
v->NoOfDPPThisState,
|
||||
v->DCCEnable,
|
||||
v->RequiredDPPCLKThisState,
|
||||
v->DETBufferSizeYThisState,
|
||||
v->DETBufferSizeCThisState,
|
||||
v->SwathHeightYThisState,
|
||||
v->SwathHeightCThisState,
|
||||
v->LBBitPerPixel,
|
||||
v->SwathWidthYThisState,
|
||||
v->SwathWidthCThisState,
|
||||
v->HRatio,
|
||||
v->HRatioChroma,
|
||||
v->vtaps,
|
||||
v->VTAPsChroma,
|
||||
v->VRatio,
|
||||
v->VRatioChroma,
|
||||
v->HTotal,
|
||||
v->PixelClock,
|
||||
v->BlendingAndTiming,
|
||||
v->BytePerPixelInDETY,
|
||||
v->BytePerPixelInDETC,
|
||||
v->DSTXAfterScaler,
|
||||
v->DSTYAfterScaler,
|
||||
v->WritebackEnable,
|
||||
v->WritebackPixelFormat,
|
||||
v->WritebackDestinationWidth,
|
||||
v->WritebackDestinationHeight,
|
||||
v->WritebackSourceHeight,
|
||||
&v->DRAMClockChangeSupport[i][j],
|
||||
&v->UrgentWatermark,
|
||||
&v->WritebackUrgentWatermark,
|
||||
&v->DRAMClockChangeWatermark,
|
||||
&v->WritebackDRAMClockChangeWatermark,
|
||||
&v->StutterExitWatermark,
|
||||
&v->StutterEnterPlusExitWatermark,
|
||||
&v->MinActiveDRAMClockChangeLatencySupported);
|
||||
&v->DRAMClockChangeSupport[i][j]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -5179,63 +4950,25 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActivePlanes,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int DPPOutputBufferPixels,
|
||||
unsigned int DETBufferSizeInKByte,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool GPUVMEnable,
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int MetaChunkSize,
|
||||
double UrgentLatency,
|
||||
double ExtraLatency,
|
||||
double WritebackLatency,
|
||||
double WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DRAMClockChangeLatency,
|
||||
double SRExitTime,
|
||||
double SREnterPlusExitTime,
|
||||
double DCFCLKDeepSleep,
|
||||
unsigned int DPPPerPlane[],
|
||||
bool DCCEnable[],
|
||||
double DPPCLK[],
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int vtaps[],
|
||||
unsigned int VTAPsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double *UrgentWatermark,
|
||||
double *WritebackUrgentWatermark,
|
||||
double *DRAMClockChangeWatermark,
|
||||
double *WritebackDRAMClockChangeWatermark,
|
||||
double *StutterExitWatermark,
|
||||
double *StutterEnterPlusExitWatermark,
|
||||
double *MinActiveDRAMClockChangeLatencySupported)
|
||||
enum clock_change_support *DRAMClockChangeSupport)
|
||||
{
|
||||
struct vba_vars_st *v = &mode_lib->vba;
|
||||
double EffectiveLBLatencyHidingY = 0;
|
||||
double EffectiveLBLatencyHidingC = 0;
|
||||
double LinesInDETY[DC__NUM_DPP__MAX] = { 0 };
|
||||
|
|
@ -5254,101 +4987,101 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
|||
double WritebackDRAMClockChangeLatencyHiding = 0;
|
||||
unsigned int k, j;
|
||||
|
||||
mode_lib->vba.TotalActiveDPP = 0;
|
||||
mode_lib->vba.TotalDCCActiveDPP = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
|
||||
if (DCCEnable[k] == true) {
|
||||
mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
|
||||
v->TotalActiveDPP = 0;
|
||||
v->TotalDCCActiveDPP = 0;
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
v->TotalActiveDPP = v->TotalActiveDPP + DPPPerPlane[k];
|
||||
if (v->DCCEnable[k] == true) {
|
||||
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + DPPPerPlane[k];
|
||||
}
|
||||
}
|
||||
|
||||
*UrgentWatermark = UrgentLatency + ExtraLatency;
|
||||
v->UrgentWatermark = UrgentLatency + ExtraLatency;
|
||||
|
||||
*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
|
||||
v->DRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->UrgentWatermark;
|
||||
|
||||
mode_lib->vba.TotalActiveWriteback = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (WritebackEnable[k] == true) {
|
||||
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
|
||||
v->TotalActiveWriteback = 0;
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (mode_lib->vba.TotalActiveWriteback <= 1) {
|
||||
*WritebackUrgentWatermark = WritebackLatency;
|
||||
if (v->TotalActiveWriteback <= 1) {
|
||||
v->WritebackUrgentWatermark = v->WritebackLatency;
|
||||
} else {
|
||||
*WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
}
|
||||
|
||||
if (mode_lib->vba.TotalActiveWriteback <= 1) {
|
||||
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
|
||||
if (v->TotalActiveWriteback <= 1) {
|
||||
v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency;
|
||||
} else {
|
||||
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
|
||||
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
|
||||
v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
|
||||
|
||||
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
|
||||
v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
|
||||
|
||||
EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
|
||||
EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
|
||||
LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
|
||||
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
|
||||
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
|
||||
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
LinesInDETC = mode_lib->vba.DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
|
||||
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
|
||||
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k];
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
|
||||
} else {
|
||||
LinesInDETC = 0;
|
||||
FullDETBufferingTimeC = 999999;
|
||||
}
|
||||
|
||||
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark;
|
||||
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
|
||||
|
||||
if (NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
|
||||
if (v->NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
|
||||
}
|
||||
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark;
|
||||
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
|
||||
|
||||
if (NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k];
|
||||
if (v->NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
|
||||
}
|
||||
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
|
||||
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
|
||||
} else {
|
||||
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
|
||||
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
|
||||
}
|
||||
|
||||
if (WritebackEnable[k] == true) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
|
||||
WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
|
||||
if (WritebackPixelFormat[k] == dm_444_64) {
|
||||
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
|
||||
if (v->WritebackPixelFormat[k] == dm_444_64) {
|
||||
WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2;
|
||||
}
|
||||
if (mode_lib->vba.WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) {
|
||||
if (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) {
|
||||
WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding * 2;
|
||||
}
|
||||
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - mode_lib->vba.WritebackDRAMClockChangeWatermark;
|
||||
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
|
||||
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
|
||||
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
|
||||
}
|
||||
}
|
||||
|
||||
mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
|
||||
v->MinActiveDRAMClockChangeMargin = 999999;
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < mode_lib->vba.MinActiveDRAMClockChangeMargin) {
|
||||
mode_lib->vba.MinActiveDRAMClockChangeMargin = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
|
||||
if (BlendingAndTiming[k] == k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
|
||||
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
|
||||
if (v->BlendingAndTiming[k] == k) {
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = k;
|
||||
} else {
|
||||
for (j = 0; j < NumberOfActivePlanes; ++j) {
|
||||
if (BlendingAndTiming[k] == j) {
|
||||
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
|
||||
if (v->BlendingAndTiming[k] == j) {
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = j;
|
||||
}
|
||||
}
|
||||
|
|
@ -5356,40 +5089,40 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
|||
}
|
||||
}
|
||||
|
||||
*MinActiveDRAMClockChangeLatencySupported = mode_lib->vba.MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
|
||||
v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->FinalDRAMClockChangeLatency;
|
||||
|
||||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
|
||||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
|
||||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
|
||||
}
|
||||
}
|
||||
|
||||
mode_lib->vba.TotalNumberOfActiveOTG = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (BlendingAndTiming[k] == k) {
|
||||
mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG + 1;
|
||||
v->TotalNumberOfActiveOTG = 0;
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->BlendingAndTiming[k] == k) {
|
||||
v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
|
||||
if (v->MinActiveDRAMClockChangeMargin > 0) {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
|
||||
} else if (((mode_lib->vba.SynchronizedVBlank == true || mode_lib->vba.TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {
|
||||
} else if (((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
|
||||
} else {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
|
||||
}
|
||||
|
||||
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0];
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
|
||||
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[k];
|
||||
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (HTotal[k] / PixelClock[k]) / VRatio[k];
|
||||
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
|
||||
}
|
||||
}
|
||||
|
||||
*StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*StutterEnterPlusExitWatermark = dml_max(SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane);
|
||||
v->StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
v->StutterEnterPlusExitWatermark = dml_max(v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1610,38 +1610,12 @@ dce110_select_crtc_source(struct pipe_ctx *pipe_ctx)
|
|||
struct dc_bios *bios = link->ctx->dc_bios;
|
||||
struct bp_crtc_source_select crtc_source_select = {0};
|
||||
enum engine_id engine_id = link->link_enc->preferred_engine;
|
||||
uint8_t bit_depth;
|
||||
|
||||
if (dc_is_rgb_signal(pipe_ctx->stream->signal))
|
||||
engine_id = link->link_enc->analog_engine;
|
||||
|
||||
switch (pipe_ctx->stream->timing.display_color_depth) {
|
||||
case COLOR_DEPTH_UNDEFINED:
|
||||
bit_depth = 0;
|
||||
break;
|
||||
case COLOR_DEPTH_666:
|
||||
bit_depth = 6;
|
||||
break;
|
||||
default:
|
||||
case COLOR_DEPTH_888:
|
||||
bit_depth = 8;
|
||||
break;
|
||||
case COLOR_DEPTH_101010:
|
||||
bit_depth = 10;
|
||||
break;
|
||||
case COLOR_DEPTH_121212:
|
||||
bit_depth = 12;
|
||||
break;
|
||||
case COLOR_DEPTH_141414:
|
||||
bit_depth = 14;
|
||||
break;
|
||||
case COLOR_DEPTH_161616:
|
||||
bit_depth = 16;
|
||||
break;
|
||||
}
|
||||
|
||||
crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst;
|
||||
crtc_source_select.bit_depth = bit_depth;
|
||||
crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth;
|
||||
crtc_source_select.engine_id = engine_id;
|
||||
crtc_source_select.sink_signal = pipe_ctx->stream->signal;
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user