From 1a35eb926d780892c6fe4e38907b62126bc98214 Mon Sep 17 00:00:00 2001 From: Dylan Hung Date: Wed, 11 May 2022 15:09:37 +0800 Subject: [PATCH] clk: ast2600: slow down the I3C core clock to 100MHz slow down I3C core clock from HCLK200M to APLL800M/8. This is aimed to enlarge the max attainable SDA hold time from 35ns (5ns * 7) to 70ns (10ns * 7). Signed-off-by: Dylan Hung Change-Id: I77310414c2f165d2a220d18d8567c07a009d97d7 --- drivers/clk/clk-ast2600.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index 0618e72cd2aa..7dbb82f7b866 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -986,6 +986,13 @@ static void __init aspeed_g6_cc(struct regmap *map) /* i3c clock */ regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val); + + /* i3c core clock 100MHz (APLL 800MHz / 8) */ + val &= ~(I3C_CLK_SELECTION | APLL_DIV_SELECTION); + val |= FIELD_PREP(I3C_CLK_SELECTION, I3C_CLK_SELECT_APLL_DIV); + val |= FIELD_PREP(APLL_DIV_SELECTION, APLL_DIV_8); + regmap_write(map, ASPEED_G6_CLK_SELECTION5, val); + if (FIELD_GET(I3C_CLK_SELECTION, val) == I3C_CLK_SELECT_APLL_DIV) { val = FIELD_GET(APLL_DIV_SELECTION, val); if (val)