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drm/amd/display: Don't use tiling flags anymore

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All supported GPU generations now support DRM format modifiers.
Remove all code from amdgpu_dm that dealt with tiling flags.

Note that the legacy non-DC display code still relies on
tiling flags, so we can't remove them outside of DC
until we also remove the legacy display code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Link Mauve <linkmauve@linkmauve.fr>
Tested-by: Nikola Medić <nmedic89@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf 2026-07-22 18:59:25 +02:00 committed by Alex Deucher
parent 3104069690
commit 1a16dfe535
4 changed files with 3 additions and 188 deletions
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8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -2917,7 +2917,6 @@ EXPORT_IF_KUNIT(fill_plane_color_attributes);
static int
fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
const struct drm_plane_state *plane_state,
const u64 tiling_flags,
struct dc_plane_info *plane_info,
struct dc_plane_address *address,
bool tmz_surface)
@ -3015,7 +3014,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
return ret;
ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
plane_info->rotation, tiling_flags,
plane_info->rotation,
&plane_info->tiling_info,
&plane_info->plane_size,
&plane_info->dcc, address,
@ -3051,7 +3050,6 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
dc_plane_state->scaling_quality = scaling_info.scaling_quality;
ret = fill_dc_plane_info_and_addr(adev, plane_state,
afb->tiling_flags,
&plane_info,
&dc_plane_state->address,
afb->tmz_surface);
@ -3878,7 +3876,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state,
fill_dc_plane_info_and_addr(
dm->adev, new_plane_state,
afb->tiling_flags,
&bundle->plane_infos[planes_count],
&bundle->flip_addrs[planes_count].address,
afb->tmz_surface);
@ -5751,8 +5748,7 @@ static bool should_reset_plane(struct drm_atomic_commit *state,
new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
/* Tiling and DCC changes also require bandwidth updates. */
if (old_afb->tiling_flags != new_afb->tiling_flags ||
old_afb->base.modifier != new_afb->base.modifier)
if (old_afb->base.modifier != new_afb->base.modifier)
return true;
}

37
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
View File

@ -211,39 +211,6 @@ STATIC_IFN_KUNIT unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_
}
EXPORT_IF_KUNIT(amdgpu_dm_plane_modifier_gfx9_swizzle_mode);
STATIC_IFN_KUNIT void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,
uint64_t tiling_flags)
{
/* Fill GFX8 params */
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
tiling_info->gfxversion = DcGfxVersion8;
/* XXX fix me for VI */
tiling_info->gfx8.num_banks = num_banks;
tiling_info->gfx8.array_mode =
DC_ARRAY_2D_TILED_THIN1;
tiling_info->gfx8.tile_split = tile_split;
tiling_info->gfx8.bank_width = bankw;
tiling_info->gfx8.bank_height = bankh;
tiling_info->gfx8.tile_aspect = mtaspect;
tiling_info->gfx8.tile_mode =
DC_ADDR_SURF_MICRO_TILING_DISPLAY;
} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
== DC_ARRAY_1D_TILED_THIN1) {
tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
}
tiling_info->gfx8.pipe_config =
AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
}
EXPORT_IF_KUNIT(amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags);
STATIC_IFN_KUNIT int amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier(
struct dc_tiling_info *tiling_info,
uint64_t modifier)
@ -1160,7 +1127,6 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
const struct amdgpu_framebuffer *afb,
const enum surface_pixel_format format,
const enum dc_rotation_angle rotation,
const uint64_t tiling_flags,
struct dc_tiling_info *tiling_info,
struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc,
@ -1235,8 +1201,6 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
address);
if (ret)
return ret;
} else if (afb->base.modifier == DRM_FORMAT_MOD_INVALID) {
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
} else {
ret = amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier(tiling_info,
afb->base.modifier);
@ -1332,7 +1296,6 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
amdgpu_dm_plane_fill_plane_buffer_attributes(
adev, afb, plane_state->format, plane_state->rotation,
afb->tiling_flags,
&plane_state->tiling_info, &plane_state->plane_size,
&plane_state->dcc, &plane_state->address,
afb->tmz_surface);

3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
View File

@ -48,7 +48,6 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
const struct amdgpu_framebuffer *afb,
const enum surface_pixel_format format,
const enum dc_rotation_angle rotation,
const uint64_t tiling_flags,
struct dc_tiling_info *tiling_info,
struct plane_size *plane_size,
struct dc_plane_dcc_param *dcc,
@ -71,8 +70,6 @@ bool amdgpu_dm_plane_is_video_format(uint32_t format);
#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_t mod);
void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,
uint64_t tiling_flags);
void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
struct dc_tiling_info *tiling_info);
void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,

143
drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
View File

@ -406,62 +406,6 @@ static void dm_test_get_min_max_dc_plane_scaling(struct kunit *test)
KUNIT_EXPECT_EQ(test, max_upscale, 1600);
}
/**
* dm_test_fill_plane_buffer_attributes_gfx8() - Verify graphics path and GFX8 tiling fill.
* @test: KUnit test context.
*
* Verify if GFX8 plane buffer attributes and tiling fields are filled correctly.
*/
static void dm_test_fill_plane_buffer_attributes_gfx8(struct kunit *test)
{
struct amdgpu_device *adev;
struct amdgpu_framebuffer *afb;
struct dc_tiling_info *tiling_info;
struct plane_size *plane_size;
struct dc_plane_dcc_param *dcc;
struct dc_plane_address *address;
uint64_t tiling_flags = 0;
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
tiling_info = kunit_kzalloc(test, sizeof(*tiling_info), GFP_KERNEL);
plane_size = kunit_kzalloc(test, sizeof(*plane_size), GFP_KERNEL);
dcc = kunit_kzalloc(test, sizeof(*dcc), GFP_KERNEL);
address = kunit_kzalloc(test, sizeof(*address), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, afb);
KUNIT_ASSERT_NOT_NULL(test, tiling_info);
KUNIT_ASSERT_NOT_NULL(test, plane_size);
KUNIT_ASSERT_NOT_NULL(test, dcc);
KUNIT_ASSERT_NOT_NULL(test, address);
adev->family = AMDGPU_FAMILY_SI;
afb->address = 0x12345000ULL;
afb->base.width = 1920;
afb->base.height = 1080;
afb->base.offsets[0] = 0x1000;
afb->base.pitches[0] = 7680;
afb->base.format = drm_format_info(DRM_FORMAT_XRGB8888);
KUNIT_ASSERT_NOT_NULL(test, afb->base.format);
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, DC_ARRAY_1D_TILED_THIN1);
tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, 5);
ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb,
SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, ROTATION_ANGLE_0,
tiling_flags, tiling_info, plane_size, dcc, address, true);
KUNIT_EXPECT_EQ(test, ret, 0);
KUNIT_EXPECT_EQ(test, plane_size->surface_size.width, 1920);
KUNIT_EXPECT_EQ(test, plane_size->surface_size.height, 1080);
KUNIT_EXPECT_EQ(test, plane_size->surface_pitch, 1920);
KUNIT_EXPECT_EQ(test, address->type, (int)PLN_ADDR_TYPE_GRAPHICS);
KUNIT_EXPECT_TRUE(test, address->tmz_surface);
KUNIT_EXPECT_EQ(test, (int)tiling_info->gfx8.array_mode, (int)DC_ARRAY_1D_TILED_THIN1);
KUNIT_EXPECT_EQ(test, tiling_info->gfx8.pipe_config, 5U);
}
/**
* dm_test_get_cursor_position() - Verify cursor clipping and off-screen handling.
* @test: KUnit test context.
@ -992,86 +936,6 @@ static void dm_test_add_modifier_noop_when_mods_null(struct kunit *test)
KUNIT_EXPECT_EQ(test, cap, 7ULL);
}
/**
* dm_test_fill_gfx8_tiling_info_2d_tiled() - Verify GFX8 2D tiled flag parsing.
* @test: KUnit test context.
*
* Verify if 2D tiled GFX8 flags populate expected tiling fields.
*/
static void dm_test_fill_gfx8_tiling_info_2d_tiled(struct kunit *test)
{
struct dc_tiling_info tiling_info = {0};
uint64_t tiling_flags = 0;
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, DC_ARRAY_2D_TILED_THIN1);
tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, 2);
tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, 1);
tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, 3);
tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, 4);
tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, 2);
tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, 7);
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(&tiling_info, tiling_flags);
KUNIT_EXPECT_EQ(test, (int)tiling_info.gfxversion, (int)DcGfxVersion8);
KUNIT_EXPECT_EQ(test, (int)tiling_info.gfx8.array_mode, (int)DC_ARRAY_2D_TILED_THIN1);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.bank_width, 2U);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.bank_height, 1U);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.tile_aspect, 3U);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.tile_split, 4U);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.num_banks, 2U);
KUNIT_EXPECT_EQ(test, (int)tiling_info.gfx8.tile_mode,
(int)DC_ADDR_SURF_MICRO_TILING_DISPLAY);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.pipe_config, 7U);
}
/**
* dm_test_fill_gfx8_tiling_info_1d_tiled() - Verify GFX8 1D tiled flag parsing.
* @test: KUnit test context.
*
* Verify if 1D tiled GFX8 flags populate array mode and pipe config.
*/
static void dm_test_fill_gfx8_tiling_info_1d_tiled(struct kunit *test)
{
struct dc_tiling_info tiling_info = {0};
uint64_t tiling_flags = 0;
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, DC_ARRAY_1D_TILED_THIN1);
tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, 5);
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(&tiling_info, tiling_flags);
KUNIT_EXPECT_EQ(test, (int)tiling_info.gfx8.array_mode, (int)DC_ARRAY_1D_TILED_THIN1);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.pipe_config, 5U);
}
/**
* dm_test_fill_gfx8_tiling_info_other_mode() - Verify non-1D/non-2D mode handling.
* @test: KUnit test context.
*
* Verify if unsupported array mode keeps preset fields and updates pipe config.
*/
static void dm_test_fill_gfx8_tiling_info_other_mode(struct kunit *test)
{
struct dc_tiling_info tiling_info = {0};
uint64_t tiling_flags = 0;
tiling_info.gfxversion = 0x7f;
tiling_info.gfx8.array_mode = 0x7f;
tiling_info.gfx8.tile_mode = 0x7f;
tiling_info.gfx8.num_banks = 0x7f;
tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, 6);
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(&tiling_info, tiling_flags);
KUNIT_EXPECT_EQ(test, tiling_info.gfxversion, 0x7f);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.array_mode, 0x7f);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.tile_mode, 0x7f);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.num_banks, 0x7f);
KUNIT_EXPECT_EQ(test, tiling_info.gfx8.pipe_config, 6U);
}
/**
* dm_test_fill_gfx9_tiling_info_from_device_pre_10_3() - Verify GFX9 field copy before 10.3.
* @test: KUnit test context.
@ -1399,7 +1263,7 @@ static int dm_test_plane_attrs(struct amdgpu_device *adev,
struct dc_plane_address *address)
{
return amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, format,
ROTATION_ANGLE_0, 0, tiling_info, plane_size, dcc, address,
ROTATION_ANGLE_0, tiling_info, plane_size, dcc, address,
false);
}
@ -3195,7 +3059,6 @@ static struct kunit_case amdgpu_dm_plane_test_cases[] = {
KUNIT_CASE(dm_test_get_min_max_dc_plane_scaling),
KUNIT_CASE(dm_test_get_min_max_dc_plane_scaling_fp16),
/* amdgpu_dm_plane_fill_plane_buffer_attributes() */
KUNIT_CASE(dm_test_fill_plane_buffer_attributes_gfx8),
KUNIT_CASE(dm_test_fill_plane_buffer_attributes_video),
KUNIT_CASE(dm_test_fill_plane_buffer_attributes_gfx12),
/* amdgpu_dm_plane_get_cursor_position() */
@ -3245,10 +3108,6 @@ static struct kunit_case amdgpu_dm_plane_test_cases[] = {
KUNIT_CASE(dm_test_add_modifier_appends_value),
KUNIT_CASE(dm_test_add_modifier_grows_capacity),
KUNIT_CASE(dm_test_add_modifier_noop_when_mods_null),
/* amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() */
KUNIT_CASE(dm_test_fill_gfx8_tiling_info_2d_tiled),
KUNIT_CASE(dm_test_fill_gfx8_tiling_info_1d_tiled),
KUNIT_CASE(dm_test_fill_gfx8_tiling_info_other_mode),
/* amdgpu_dm_plane_fill_gfx9_tiling_info_from_device() */
KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_pre_10_3),
KUNIT_CASE(dm_test_fill_gfx9_tiling_info_from_device_10_3_plus),