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arm64: dts: qcom: sc8280xp: add p1 register blocks to DP nodes

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Per DT bindings add p1 register blocks to all DP controllers on SC8280XP
platform.

Fixes: 6f299ae7f96d ("arm64: dts: qcom: sc8280xp: add p1 register blocks to DP nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230118031718.1714861-4-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-01-18 05:17:18 +02:00 committed by Bjorn Andersson
parent 3cfa9e245d
commit 19eee67386
1 changed files with 12 additions and 6 deletions
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18
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
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@ -3204,7 +3204,8 @@ mdss0_dp2: displayport-controller@ae9a000 {
reg = <0 0xae9a000 0 0x200>,
<0 0xae9a200 0 0x200>,
<0 0xae9a400 0 0x600>,
<0 0xae9b000 0 0x400>;
<0 0xae9b000 0 0x400>,
<0 0xae9b400 0 0x400>;
clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
@ -3275,7 +3276,8 @@ mdss0_dp3: displayport-controller@aea0000 {
reg = <0 0xaea0000 0 0x200>,
<0 0xaea0200 0 0x200>,
<0 0xaea0400 0 0x600>,
<0 0xaea1000 0 0x400>;
<0 0xaea1000 0 0x400>,
<0 0xaea1400 0 0x400>;
clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
@ -4150,7 +4152,8 @@ mdss1_dp0: displayport-controller@22090000 {
reg = <0 0x22090000 0 0x200>,
<0 0x22090200 0 0x200>,
<0 0x22090400 0 0x600>,
<0 0x22091000 0 0x400>;
<0 0x22091000 0 0x400>,
<0 0x22091400 0 0x400>;
clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
@ -4222,7 +4225,8 @@ mdss1_dp1: displayport-controller@22098000 {
reg = <0 0x22098000 0 0x200>,
<0 0x22098200 0 0x200>,
<0 0x22098400 0 0x600>,
<0 0x22099000 0 0x400>;
<0 0x22099000 0 0x400>,
<0 0x22099400 0 0x400>;
clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
@ -4293,7 +4297,8 @@ mdss1_dp2: displayport-controller@2209a000 {
reg = <0 0x2209a000 0 0x200>,
<0 0x2209a200 0 0x200>,
<0 0x2209a400 0 0x600>,
<0 0x2209b000 0 0x400>;
<0 0x2209b000 0 0x400>,
<0 0x2209b400 0 0x400>;
clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
@ -4364,7 +4369,8 @@ mdss1_dp3: displayport-controller@220a0000 {
reg = <0 0x220a0000 0 0x200>,
<0 0x220a0200 0 0x200>,
<0 0x220a0400 0 0x600>,
<0 0x220a1000 0 0x400>;
<0 0x220a1000 0 0x400>,
<0 0x220a1400 0 0x400>;
clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,