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drm/xe/dg2: Fix using wrong PAT table

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DG2 should use the MCR variant to program the PAT registers, like PVC,
but shouldn't use the same table as PVC.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230927193902.2849159-7-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-09-27 12:38:57 -07:00 committed by Rodrigo Vivi
parent b445be5710
commit 194bdb8599
1 changed files with 9 additions and 1 deletions
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10
drivers/gpu/drm/xe/xe_pat.c
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@ -108,10 +108,18 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.ops = &mtl_pat_ops;
xe->pat.table = mtl_pat_table;
xe->pat.n_entries = ARRAY_SIZE(mtl_pat_table);
} else if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2) {
} else if (xe->info.platform == XE_PVC) {
xe->pat.ops = &dg2_pat_ops;
xe->pat.table = pvc_pat_table;
xe->pat.n_entries = ARRAY_SIZE(pvc_pat_table);
} else if (xe->info.platform == XE_DG2) {
/*
* Table is the same as previous platforms, but programming
* method has changed.
*/
xe->pat.ops = &dg2_pat_ops;
xe->pat.table = tgl_pat_table;
xe->pat.n_entries = ARRAY_SIZE(tgl_pat_table);
} else if (GRAPHICS_VERx100(xe) <= 1210) {
xe->pat.ops = &tgl_pat_ops;
xe->pat.table = tgl_pat_table;