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soc/tegra: pmc: Fix imbalanced clock disabling in error code path

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The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2021-03-02 15:24:58 +03:00 committed by Thierry Reding
parent ef85bb582c
commit 19221e3083
1 changed files with 1 additions and 1 deletions
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2
drivers/soc/tegra/pmc.c
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@ -660,7 +660,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,
err = tegra_powergate_enable_clocks(pg);
if (err)
goto disable_clks;
goto powergate_off;
usleep_range(10, 20);