arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 node

This board has one Type-C port which has USB3 capability. This will
add typec nodes and enable usb3 node.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Xu Yang 2024-12-04 13:09:07 +08:00 committed by Shawn Guo
parent 8e2fae4e28
commit 18e5ff7aab

View File

@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
#define FALLING_EDGE 1
@ -317,6 +318,48 @@ i2c7_pcal6524: i2c7-gpio@22 {
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio5>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&lpuart1 {
@ -418,6 +461,40 @@ &sai3 {
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
role-switch-default-mode = "peripheral";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3_phy {
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
orientation-switch;
status = "okay";
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -676,6 +753,12 @@ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e