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drm/amd/display: Fix index may exceed array range within fpu_update_bw_bounding_box

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[Why]
Coverity reports OVERRUN warning. soc.num_states could
be 40. But array range of bw_params->clk_table.entries is 8.

[How]
Assert if soc.num_states greater than 8.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hersen Wu 2024-04-25 09:24:44 -04:00 committed by Alex Deucher
parent 922c287782
commit 188fd1616e
4 changed files with 40 additions and 0 deletions
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10
drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
View File

@ -304,6 +304,16 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
* MAX_NUM_DPM_LVL is 8.
* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
* DC__VOLTAGE_STATES is 40.
*/
if (num_states > MAX_NUM_DPM_LVL) {
ASSERT(0);
return;
}
dcn3_02_soc.num_states = num_states;
for (i = 0; i < dcn3_02_soc.num_states; i++) {
dcn3_02_soc.clock_limits[i].state = i;

10
drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
View File

@ -310,6 +310,16 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
* MAX_NUM_DPM_LVL is 8.
* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
* DC__VOLTAGE_STATES is 40.
*/
if (num_states > MAX_NUM_DPM_LVL) {
ASSERT(0);
return;
}
dcn3_03_soc.num_states = num_states;
for (i = 0; i < dcn3_03_soc.num_states; i++) {
dcn3_03_soc.clock_limits[i].state = i;

10
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@ -3232,6 +3232,16 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
* MAX_NUM_DPM_LVL is 8.
* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
* DC__VOLTAGE_STATES is 40.
*/
if (num_states > MAX_NUM_DPM_LVL) {
ASSERT(0);
return;
}
dcn3_2_soc.num_states = num_states;
for (i = 0; i < dcn3_2_soc.num_states; i++) {
dcn3_2_soc.clock_limits[i].state = i;

10
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
View File

@ -803,6 +803,16 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
* MAX_NUM_DPM_LVL is 8.
* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
* DC__VOLTAGE_STATES is 40.
*/
if (num_states > MAX_NUM_DPM_LVL) {
ASSERT(0);
return;
}
dcn3_21_soc.num_states = num_states;
for (i = 0; i < dcn3_21_soc.num_states; i++) {
dcn3_21_soc.clock_limits[i].state = i;