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drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation

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The encoder state computation should use the
drm_display_mode::crtc_clock member, instead of the clock member, the
former one possibly having a necessary adjustment wrt. to the latter
due to driver specific constraints. In practice the two values should
not differ at spots changed in this patch, since only MSO and 3D modes
would make them different, neither MSO or 3D relevant here, but still
use the expected crtc_clock version for consistency.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-6-imre.deak@intel.com
This commit is contained in:
Imre Deak 2025-12-15 21:23:45 +02:00
parent 1f28404ad4
commit 1867564b90
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/i915/display/intel_dp.c
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@ -2051,7 +2051,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
continue;
} else {
if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate,
lane_count, adjusted_mode->clock,
lane_count,
adjusted_mode->crtc_clock,
pipe_config->output_format,
timeslots))
continue;
@ -2212,7 +2213,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int bpp_x16;
int ret;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->crtc_clock,
adjusted_mode->hdisplay,
num_joined_pipes);
max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16);