github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-24 07:03:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/msm/dsi/phy: rename DSI_PHY_7NM_QUIRK_PRE_V4_1 to DSI_PHY_7NM_QUIRK_V4_0

Browse Source 
The quirk flag DSI_PHY_7NM_QUIRK_PRE_V4_1 is renamed to
DSI_PHY_7NM_QUIRK_V4_0 to better reflect the actual hardware revision
it applies to. (Only SM8150 uses it, its hardware revision is 4.0)

No functional change.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707416/
Link: https://lore.kernel.org/r/20260226122958.22555-3-mitltlatltl@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Pengyu Luo 2026-02-26 20:29:58 +08:00 committed by Dmitry Baryshkov
parent 7fe04c7c43
commit 18417122d6
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
View File

@ -41,8 +41,8 @@
#define VCO_REF_CLK_RATE 19200000
#define FRAC_BITS 18
/* Hardware is pre V4.1 */
#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
/* Hardware is V4.0 */
#define DSI_PHY_7NM_QUIRK_V4_0 BIT(0)
/* Hardware is V4.1 */
#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
/* Hardware is V4.2 */
@ -141,7 +141,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
dec_multiple = div_u64(pll_freq * multiplier, divider);
dec = div_u64_rem(dec_multiple, multiplier, &frac);
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) {
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) {
config->pll_clock_inverters = 0x28;
} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_2)) {
if (pll_freq < 163000000ULL)
@ -264,7 +264,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
void __iomem *base = pll->phy->pll_base;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0))
if (pll->vco_current_rate >= 3100000000ULL)
analog_controls_five_1 = 0x03;
@ -313,10 +313,10 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT);
writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT);
writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT);
writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22,
writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0) ? 0x3f : 0x22,
base + REG_DSI_7nm_PHY_PLL_IFILT);
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0)) {
writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
if (pll->slave)
writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
@ -928,7 +928,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
const u8 *tx_dctrl = tx_dctrl_0;
void __iomem *lane_base = phy->lane_base;
if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_0))
tx_dctrl = tx_dctrl_1;
/* Strength ctrl settings */
@ -1319,7 +1319,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
.quirks = DSI_PHY_7NM_QUIRK_V4_0,
};
const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {