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ASoC: SOF: Intel: add support for Nova Lake NVL
Add support for Nova Lake (NVL). The core count for NVL is different compared to NVL-S (4 vs 2) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Takashi Iwai <tiwai@suse.de> Link: https://patch.msgid.link/20260120193507.14019-3-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -936,6 +936,7 @@ extern const struct sof_intel_dsp_desc arl_s_chip_info;
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extern const struct sof_intel_dsp_desc lnl_chip_info;
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extern const struct sof_intel_dsp_desc ptl_chip_info;
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extern const struct sof_intel_dsp_desc wcl_chip_info;
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extern const struct sof_intel_dsp_desc nvl_chip_info;
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extern const struct sof_intel_dsp_desc nvl_s_chip_info;
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/* Probes support */
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@ -26,6 +26,30 @@ int sof_nvl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops)
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};
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EXPORT_SYMBOL_NS(sof_nvl_set_ops, "SND_SOC_SOF_INTEL_NVL");
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const struct sof_intel_dsp_desc nvl_chip_info = {
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.cores_num = 4,
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.init_core_mask = BIT(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = MTL_DSP_REG_HFIPCXIDR,
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.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = LNL_DSP_REG_HFDSC,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.d0i3_offset = MTL_HDA_VS_D0I3C,
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.read_sdw_lcount = hda_sdw_check_lcount_ext,
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.check_sdw_irq = lnl_dsp_check_sdw_irq,
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.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
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.sdw_process_wakeen = hda_sdw_process_wakeen_common,
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.check_ipc_irq = mtl_dsp_check_ipc_irq,
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.cl_init = mtl_dsp_cl_init,
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.power_down_dsp = mtl_power_down_dsp,
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.disable_interrupts = lnl_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_ACE_4_0,
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};
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const struct sof_intel_dsp_desc nvl_s_chip_info = {
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.cores_num = 2,
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.init_core_mask = BIT(0),
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@ -26,6 +26,36 @@ static int sof_nvl_ops_init(struct snd_sof_dev *sdev)
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return sof_nvl_set_ops(sdev, &sof_nvl_ops);
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}
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static const struct sof_dev_desc nvl_desc = {
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.use_acpi_target_states = true,
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.machines = snd_soc_acpi_intel_nvl_machines,
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.alt_machines = snd_soc_acpi_intel_nvl_sdw_machines,
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.resindex_lpe_base = 0,
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.resindex_pcicfg_base = -1,
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.resindex_imr_base = -1,
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.irqindex_host_ipc = -1,
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.chip_info = &nvl_chip_info,
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.ipc_supported_mask = BIT(SOF_IPC_TYPE_4),
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.ipc_default = SOF_IPC_TYPE_4,
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.dspless_mode_supported = true,
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.on_demand_dsp_boot = true,
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.default_fw_path = {
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[SOF_IPC_TYPE_4] = "intel/sof-ipc4/nvl",
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},
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.default_lib_path = {
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[SOF_IPC_TYPE_4] = "intel/sof-ipc4-lib/nvl",
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},
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.default_tplg_path = {
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[SOF_IPC_TYPE_4] = "intel/sof-ipc4-tplg",
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},
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.default_fw_filename = {
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[SOF_IPC_TYPE_4] = "sof-nvl.ri",
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},
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.nocodec_tplg_filename = "sof-nvl-nocodec.tplg",
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.ops = &sof_nvl_ops,
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.ops_init = sof_nvl_ops_init,
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};
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static const struct sof_dev_desc nvl_s_desc = {
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.use_acpi_target_states = true,
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.machines = snd_soc_acpi_intel_nvl_machines,
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@ -58,6 +88,7 @@ static const struct sof_dev_desc nvl_s_desc = {
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/* PCI IDs */
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static const struct pci_device_id sof_pci_ids[] = {
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{ PCI_DEVICE_DATA(INTEL, HDA_NVL, &nvl_desc) }, /* NVL */
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{ PCI_DEVICE_DATA(INTEL, HDA_NVL_S, &nvl_s_desc) }, /* NVL-S */
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{ 0, }
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};
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