github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-30 10:04:04 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

i.MX ARM device tree changes for 7.1:

Browse Source 
- Device Tree Schema Compliance Fixes
 
   Fixed numerous CHECK_DTBS warnings across multiple i.MX SoC families
   Renamed nodes to match schema requirements (tcq→touchscreen,
   uart8250→serial, iomuxc→pinmux, etc.). Fixed node naming conventions
   (added "led-" prefix, proper addressing formats).
 
   Corrected compatible strings and removed undocumented fallbacks. Added
   required properties (clocks, clock-names, power supplies,
   #sound-dai-cells).
 
 - New Hardware Support
 
   Added DT overlays for various expansion modules (i.MX6 DHCOM PDK2,
   PicoITX display boards). Added support for muRata 1YN WiFi chip
   (replacement for 1DX) on i.MX6ULL DHCOR board.
 
   i.MX7ULP: Added CPU clock and OPP table support for frequency scaling.
 
 - Boot Phase Properties
   Added bootph.yaml properties to multiple TQ-Systems boards and SoCs:
   imx7s, tqma7, mba7 imx6ul/ull, tqma6ul/ull, mba6ulx imx6qdl, tqma6, mba6.
 
 - Bug Fixes & Corrections
 
   Fixed interrupt property usage (interrupts→interrupts-extended where
   needed). Corrected spelling ("TQ-Systems" with hyphen). Removed redundant
   intermediate nodes in pinmux hierarchy. Fixed clock references and
   naming.
 -----BEGIN PGP SIGNATURE-----
 
 iQHFBAABCgAvFiEEJS45w2QNr0ezLVaoNF3oRQ23YkwFAmnTEUYRHGZyYW5rLmxp
 QG54cC5jb20ACgkQNF3oRQ23YkzB/Av/TwMmAG81S/lO9YuCnfTekicj4PSI3F/W
 GN4ijb+5I8x9T6UyQQnq87zvMr74eD9FS16shsuT9fQ2omHRvCOrPd36UUiZeaDU
 sAgvWvjzcsbZ2DIGgiPL6RyuBscnAkheGwYnhdm6xCkfogH8ej8uoiMBt0eCCqQm
 YUyqS9HHX7D9rHvnC/mnedXRg3N9J0X5vuq7xc+enxXa105+1FaDqrhPDfS7oBeM
 4gApl3wAApmfaicQrMAZ+rtyiB1SdE1km1zJBUDjIglNZQuj02VdQwoNwF8Tn9ca
 Qm3ondEvpV9spLQC54hPrzJ/dI2v7hqYWSqK6Q7IJb8Rosk5bN2AMehzHWnDPkfH
 7bBK79JuBCV3DcjQ8tr9FqqW1UgGsZw9Z3zPDJpbQQW42VOcgxLELpBf4rdZqSl0
 KxNkK26/gJG5jgs/RiXqtz6JeBp3CbHfzAZ8WnpujldJqOG2Wvt9TO8OJQZedaqm
 VwsvSQkGBbOKLVyvzO67VkFCvCfL/HLJ
 =vWpp
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt

i.MX ARM device tree changes for 7.1:

- Device Tree Schema Compliance Fixes

  Fixed numerous CHECK_DTBS warnings across multiple i.MX SoC families
  Renamed nodes to match schema requirements (tcq→touchscreen,
  uart8250→serial, iomuxc→pinmux, etc.). Fixed node naming conventions
  (added "led-" prefix, proper addressing formats).

  Corrected compatible strings and removed undocumented fallbacks. Added
  required properties (clocks, clock-names, power supplies,
  #sound-dai-cells).

- New Hardware Support

  Added DT overlays for various expansion modules (i.MX6 DHCOM PDK2,
  PicoITX display boards). Added support for muRata 1YN WiFi chip
  (replacement for 1DX) on i.MX6ULL DHCOR board.

  i.MX7ULP: Added CPU clock and OPP table support for frequency scaling.

- Boot Phase Properties
  Added bootph.yaml properties to multiple TQ-Systems boards and SoCs:
  imx7s, tqma7, mba7 imx6ul/ull, tqma6ul/ull, mba6ulx imx6qdl, tqma6, mba6.

- Bug Fixes & Corrections

  Fixed interrupt property usage (interrupts→interrupts-extended where
  needed). Corrected spelling ("TQ-Systems" with hyphen). Removed redundant
  intermediate nodes in pinmux hierarchy. Fixed clock references and
  naming.

* tag 'imx-dt-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (43 commits)
  ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards
  ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif
  ARM: dts: imx25: rename node name tcq to touchscreen
  ARM: dts: imx: b850v3: Disable unused usdhc4
  ARM: dts: imx: b850v3: Define GPIO line names
  ARM: dts: imx: b850v3: Use alphabetical sorting
  ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning
  ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps
  ARM: dts: imx7ulp: Add CPU clock and OPP table support
  ARM: dts: imx7-mba7: Deassert BOOT_EN after boot
  ARM: dts: tqma7: add boot phase properties
  ARM: dts: imx7s: add boot phase properties
  ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems
  ARM: dts: mba6ulx: add boot phase properties
  ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
  ARM: dts: imx6ul/imx6ull: add boot phase properties
  ARM: dts: imx6qdl-mba6: add boot phase properties
  ARM: dts: imx6qdl-tqma6: add boot phase properties
  ARM: dts: imx6qdl: add boot phase properties
  ARM: dts: imx6qdl-tqma6: add missing labels
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-04-11 10:20:17 +02:00
commit 17ed8fd2fa
89 changed files with 1596 additions and 1129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
arch/arm/boot/dts/nxp/imx/Makefile
View File

@ -58,6 +58,31 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-voipac-bsb.dtb
imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo
imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo
imx6qdl-dhcom-pdk2-overlay-497-200-x12-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo
imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo
imx6qdl-dhcom-pdk2-overlay-531-100-x21-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo
imx6qdl-dhcom-pdk2-overlay-531-100-x22-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo
imx6qdl-dhcom-pdk2-overlay-560-200-x12-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo
imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-alti6p.dtb \
imx6dl-apf6dev.dtb \
@ -179,6 +204,18 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-cubox-i-som-v15.dtb \
imx6q-dfi-fs700-m60.dtb \
imx6q-dhcom-pdk2.dtb \
imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtb \
imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo \
imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \
imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtb \
imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo \
imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtb \
imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo \
imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtb \
imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo \
imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \
imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
imx6q-display5-tianma-tm070-1280x768.dtb \
imx6q-dmo-edmqmx6.dtb \
imx6q-dms-ba16.dtb \

100
arch/arm/boot/dts/nxp/imx/imx1-ads.dts
View File

@ -76,60 +76,58 @@ nor: flash@0,0 {
};
&iomuxc {
imx1-ads {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
MX1_PAD_SPI1_SS__GPIO3_15 0x0
>;
};
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
MX1_PAD_SPI1_SS__GPIO3_15 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};

92
arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
View File

@ -67,56 +67,54 @@ eth: ethernet@4,c00000 {
};
&iomuxc {
imx1-apf9328 {
pinctrl_eth: ethgrp {
fsl,pins = <
MX1_PAD_SIM_SVEN__GPIO2_14 0x0
>;
};
pinctrl_eth: ethgrp {
fsl,pins = <
MX1_PAD_SIM_SVEN__GPIO2_14 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx1.dtsi
View File

@ -202,7 +202,7 @@ clks: ccm@21b000 {
#clock-cells = <1>;
};
iomuxc: iomuxc@21c000 {
iomuxc: pinmux@21c000 {
compatible = "fsl,imx1-iomuxc";
reg = <0x0021c000 0x1000>;
#address-cells = <1>;

38
arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi
View File

@ -34,27 +34,25 @@ rtc@51 {
};
&iomuxc {
imx25-eukrea-cpuimx25 {
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
};

6
arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
View File

@ -43,10 +43,8 @@ reg_lcd_3v3: regulator-0 {
};
&iomuxc {
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
};
pinctrl_reg_lcd_3v3: reg_lcd_3v3grp {
fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
};
};

134
arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts
View File

@ -68,80 +68,78 @@ tlv320aic23: codec@1a {
};
&iomuxc {
imx25-eukrea-mbimxsd25-baseboard {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0
>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
};
pinctrl_lcdc: lcdcgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0x1
MX25_PAD_LD1__LD1 0x1
MX25_PAD_LD2__LD2 0x1
MX25_PAD_LD3__LD3 0x1
MX25_PAD_LD4__LD4 0x1
MX25_PAD_LD5__LD5 0x1
MX25_PAD_LD6__LD6 0x1
MX25_PAD_LD7__LD7 0x1
MX25_PAD_LD8__LD8 0x1
MX25_PAD_LD9__LD9 0x1
MX25_PAD_LD10__LD10 0x1
MX25_PAD_LD11__LD11 0x1
MX25_PAD_LD12__LD12 0x1
MX25_PAD_LD13__LD13 0x1
MX25_PAD_LD14__LD14 0x1
MX25_PAD_LD15__LD15 0x1
MX25_PAD_GPIO_E__LD16 0x1
MX25_PAD_GPIO_F__LD17 0x1
MX25_PAD_HSYNC__HSYNC 0x80000000
MX25_PAD_VSYNC__VSYNC 0x80000000
MX25_PAD_LSCLK__LSCLK 0x80000000
MX25_PAD_OE_ACD__OE_ACD 0x80000000
MX25_PAD_CONTRAST__CONTRAST 0x80000000
>;
};
pinctrl_lcdc: lcdcgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0x1
MX25_PAD_LD1__LD1 0x1
MX25_PAD_LD2__LD2 0x1
MX25_PAD_LD3__LD3 0x1
MX25_PAD_LD4__LD4 0x1
MX25_PAD_LD5__LD5 0x1
MX25_PAD_LD6__LD6 0x1
MX25_PAD_LD7__LD7 0x1
MX25_PAD_LD8__LD8 0x1
MX25_PAD_LD9__LD9 0x1
MX25_PAD_LD10__LD10 0x1
MX25_PAD_LD11__LD11 0x1
MX25_PAD_LD12__LD12 0x1
MX25_PAD_LD13__LD13 0x1
MX25_PAD_LD14__LD14 0x1
MX25_PAD_LD15__LD15 0x1
MX25_PAD_GPIO_E__LD16 0x1
MX25_PAD_GPIO_F__LD17 0x1
MX25_PAD_HSYNC__HSYNC 0x80000000
MX25_PAD_VSYNC__VSYNC 0x80000000
MX25_PAD_LSCLK__LSCLK 0x80000000
MX25_PAD_OE_ACD__OE_ACD 0x80000000
MX25_PAD_CONTRAST__CONTRAST 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX25_PAD_UART2_RXD__UART2_RXD 0x80000000
MX25_PAD_UART2_TXD__UART2_TXD 0x80000000
MX25_PAD_UART2_RTS__UART2_RTS 0x80000000
MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX25_PAD_UART2_RXD__UART2_RXD 0x80000000
MX25_PAD_UART2_TXD__UART2_TXD 0x80000000
MX25_PAD_UART2_RTS__UART2_RTS 0x80000000
MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
>;
};
};

190
arch/arm/boot/dts/nxp/imx/imx25-pdk.dts
View File

@ -130,109 +130,107 @@ codec: sgtl5000@a {
};
&iomuxc {
imx25-pdk {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_RW__AUD4_TXFS 0xe0
MX25_PAD_OE__AUD4_TXC 0xe0
MX25_PAD_EB0__AUD4_TXD 0xe0
MX25_PAD_EB1__AUD4_RXD 0xe0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX25_PAD_RW__AUD4_TXFS 0xe0
MX25_PAD_OE__AUD4_TXC 0xe0
MX25_PAD_EB0__AUD4_TXD 0xe0
MX25_PAD_EB1__AUD4_RXD 0xe0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX25_PAD_GPIO_A__CAN1_TX 0x0
MX25_PAD_GPIO_B__CAN1_RX 0x0
MX25_PAD_D14__GPIO_4_6 0x80000000
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX25_PAD_GPIO_A__CAN1_TX 0x0
MX25_PAD_GPIO_B__CAN1_RX 0x0
MX25_PAD_D14__GPIO_4_6 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX25_PAD_A14__GPIO_2_0 0x80000000
MX25_PAD_A15__GPIO_2_1 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX25_PAD_A14__GPIO_2_0 0x80000000
MX25_PAD_A15__GPIO_2_1 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
MX25_PAD_A17__GPIO_2_3 0x80000000
MX25_PAD_D12__GPIO_4_8 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
MX25_PAD_A17__GPIO_2_3 0x80000000
MX25_PAD_D12__GPIO_4_8 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0xe0
MX25_PAD_LD1__LD1 0xe0
MX25_PAD_LD2__LD2 0xe0
MX25_PAD_LD3__LD3 0xe0
MX25_PAD_LD4__LD4 0xe0
MX25_PAD_LD5__LD5 0xe0
MX25_PAD_LD6__LD6 0xe0
MX25_PAD_LD7__LD7 0xe0
MX25_PAD_LD8__LD8 0xe0
MX25_PAD_LD9__LD9 0xe0
MX25_PAD_LD10__LD10 0xe0
MX25_PAD_LD11__LD11 0xe0
MX25_PAD_LD12__LD12 0xe0
MX25_PAD_LD13__LD13 0xe0
MX25_PAD_LD14__LD14 0xe0
MX25_PAD_LD15__LD15 0xe0
MX25_PAD_GPIO_E__LD16 0xe0
MX25_PAD_GPIO_F__LD17 0xe0
MX25_PAD_HSYNC__HSYNC 0xe0
MX25_PAD_VSYNC__VSYNC 0xe0
MX25_PAD_LSCLK__LSCLK 0xe0
MX25_PAD_OE_ACD__OE_ACD 0xe0
MX25_PAD_CONTRAST__CONTRAST 0xe0
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0xe0
MX25_PAD_LD1__LD1 0xe0
MX25_PAD_LD2__LD2 0xe0
MX25_PAD_LD3__LD3 0xe0
MX25_PAD_LD4__LD4 0xe0
MX25_PAD_LD5__LD5 0xe0
MX25_PAD_LD6__LD6 0xe0
MX25_PAD_LD7__LD7 0xe0
MX25_PAD_LD8__LD8 0xe0
MX25_PAD_LD9__LD9 0xe0
MX25_PAD_LD10__LD10 0xe0
MX25_PAD_LD11__LD11 0xe0
MX25_PAD_LD12__LD12 0xe0
MX25_PAD_LD13__LD13 0xe0
MX25_PAD_LD14__LD14 0xe0
MX25_PAD_LD15__LD15 0xe0
MX25_PAD_GPIO_E__LD16 0xe0
MX25_PAD_GPIO_F__LD17 0xe0
MX25_PAD_HSYNC__HSYNC 0xe0
MX25_PAD_VSYNC__VSYNC 0xe0
MX25_PAD_LSCLK__LSCLK 0xe0
MX25_PAD_OE_ACD__OE_ACD 0xe0
MX25_PAD_CONTRAST__CONTRAST 0xe0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
>;
};
};

4
arch/arm/boot/dts/nxp/imx/imx25.dtsi
View File

@ -195,7 +195,7 @@ kpp: kpp@43fa8000 {
status = "disabled";
};
iomuxc: iomuxc@43fac000 {
iomuxc: pinmux@43fac000 {
compatible = "fsl,imx25-iomuxc";
reg = <0x43fac000 0x4000>;
};
@ -305,7 +305,7 @@ adc: adc@50030800 {
status = "disabled";
};
tsc: tcq@50030400 {
tsc: touchscreen@50030400 {
compatible = "fsl,imx25-tcq";
reg = <0x50030400 0x60>;
interrupt-parent = <&tscadc>;

56
arch/arm/boot/dts/nxp/imx/imx27-apf27.dts
View File

@ -24,36 +24,34 @@ &clk_osc26m {
};
&iomuxc {
imx27-apf27 {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
>;
};
};

194
arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts
View File

@ -122,116 +122,114 @@ &i2c2 {
};
&iomuxc {
imx27-apf27dev {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
>;
};
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
>;
};
pinctrl_cspi1_cs: cspi1csgrp {
fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
};
pinctrl_cspi1_cs: cspi1csgrp {
fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
};
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
>;
};
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
>;
};
pinctrl_cspi2_cs: cspi2csgrp {
fsl,pins = <
MX27_PAD_CSI_D5__GPIO2_17 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_cspi2_cs: cspi2csgrp {
fsl,pins = <
MX27_PAD_CSI_D5__GPIO2_17 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_max1027: max1027 {
fsl,pins = <
MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
>;
};
pinctrl_max1027: max1027grp {
fsl,pins = <
MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
>;
};
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0
>;
};
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_sdhc2_cd: sdhc2cdgrp {
fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
};
pinctrl_sdhc2_cd: sdhc2cdgrp {
fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
};
};

244
arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi
View File

@ -100,52 +100,52 @@ nor: flash@0,0 {
fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
};
uart8250@3,200000 {
serial@3,200000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_1>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x200000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,400000 {
serial@3,400000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_2>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x400000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,800000 {
serial@3,800000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_3>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x800000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
no-loopback-test;
};
uart8250@3,1000000 {
serial@3,1000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8250_4>;
compatible = "ns8250";
clocks = <&clk14745600>;
fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
reg = <3 0x1000000 0x1000>;
reg-shift = <1>;
reg-io-width = <1>;
@ -154,131 +154,129 @@ uart8250@3,1000000 {
};
&iomuxc {
imx27-eukrea-cpuimx27 {
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_owire: owiregrp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_owire: owiregrp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
MX27_PAD_USBH1_FS__UART4_RTS 0x0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
MX27_PAD_USBH1_FS__UART4_RTS 0x0
>;
};
pinctrl_uart8250_1: uart82501grp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0
>;
};
pinctrl_uart8250_1: uart82501grp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0
>;
};
pinctrl_uart8250_2: uart82502grp {
fsl,pins = <
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
>;
};
pinctrl_uart8250_2: uart82502grp {
fsl,pins = <
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
>;
};
pinctrl_uart8250_3: uart82503grp {
fsl,pins = <
MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
>;
};
pinctrl_uart8250_3: uart82503grp {
fsl,pins = <
MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
>;
};
pinctrl_uart8250_4: uart82504grp {
fsl,pins = <
MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
>;
};
pinctrl_uart8250_4: uart82504grp {
fsl,pins = <
MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
};

196
arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
View File

@ -76,7 +76,7 @@ ads7846@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
reg = <0>;
interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
spi-cpol;
spi-max-frequency = <1500000>;
ti,keep-vref-on;
@ -147,113 +147,111 @@ &uart3 {
};
&iomuxc {
imx27-eukrea-cpuimx27-baseboard {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */
>;
};
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX27_PAD_PWMO__GPIO5_5 0x0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX27_PAD_PWMO__GPIO5_5 0x0
>;
};
pinctrl_gpioleds: gpioledsgrp {
fsl,pins = <
MX27_PAD_PC_PWRON__GPIO6_16 0x0
MX27_PAD_PC_CD2_B__GPIO6_19 0x0
>;
};
pinctrl_gpioleds: gpioledsgrp {
fsl,pins = <
MX27_PAD_PC_PWRON__GPIO6_16 0x0
MX27_PAD_PC_CD2_B__GPIO6_19 0x0
>;
};
pinctrl_imxfb: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_imxfb: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_lcdreg: lcdreggrp {
fsl,pins = <
MX27_PAD_CLS__GPIO1_25 0x0
>;
};
pinctrl_lcdreg: lcdreggrp {
fsl,pins = <
MX27_PAD_CLS__GPIO1_25 0x0
>;
};
pinctrl_sdhc1: sdhc1grp {
fsl,pins = <
MX27_PAD_SD1_CLK__SD1_CLK 0x0
MX27_PAD_SD1_CMD__SD1_CMD 0x0
MX27_PAD_SD1_D0__SD1_D0 0x0
MX27_PAD_SD1_D1__SD1_D1 0x0
MX27_PAD_SD1_D2__SD1_D2 0x0
MX27_PAD_SD1_D3__SD1_D3 0x0
>;
};
pinctrl_sdhc1: sdhc1grp {
fsl,pins = <
MX27_PAD_SD1_CLK__SD1_CLK 0x0
MX27_PAD_SD1_CMD__SD1_CMD 0x0
MX27_PAD_SD1_D0__SD1_D0 0x0
MX27_PAD_SD1_D1__SD1_D1 0x0
MX27_PAD_SD1_D2__SD1_D2 0x0
MX27_PAD_SD1_D3__SD1_D3 0x0
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI4_CLK__SSI4_CLK 0x0
MX27_PAD_SSI4_FS__SSI4_FS 0x0
MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1
MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI4_CLK__SSI4_CLK 0x0
MX27_PAD_SSI4_FS__SSI4_FS 0x0
MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1
MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};

132
arch/arm/boot/dts/nxp/imx/imx27-pdk.dts
View File

@ -110,76 +110,74 @@ &usbotg {
};
&iomuxc {
imx27-pdk {
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */
MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */
>;
};
pinctrl_cspi2: cspi2grp {
fsl,pins = <
MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */
MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_nand: nandgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
};

92
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts
View File

@ -65,58 +65,56 @@ adc@64 {
};
&iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};

162
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
View File

@ -58,94 +58,92 @@ eeprom@52 {
};
&iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_usbotgphy: usbotgphygrp {
fsl,pins = <
MX27_PAD_USBH1_RCV__GPIO2_25 0x1 /* reset gpio */
>;
};
pinctrl_usbotgphy: usbotgphygrp {
fsl,pins = <
MX27_PAD_USBH1_RCV__GPIO2_25 0x1 /* reset gpio */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
pinctrl_usbh2phy: usbh2phygrp {
fsl,pins = <
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 /* reset gpio */
>;
};
pinctrl_usbh2phy: usbh2phygrp {
fsl,pins = <
MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 /* reset gpio */
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
};

206
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
View File

@ -89,119 +89,117 @@ camgpio: pca9536@41 {
};
&iomuxc {
imx27_phycore_rdk {
pinctrl_csien: csiengrp {
fsl,pins = <
MX27_PAD_USB_OC_B__GPIO2_24 0x0
>;
};
pinctrl_csien: csiengrp {
fsl,pins = <
MX27_PAD_USB_OC_B__GPIO2_24 0x0
>;
};
pinctrl_cspi1cs1: cspi1cs1grp {
fsl,pins = <
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_cspi1cs1: cspi1cs1grp {
fsl,pins = <
MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_imxfb1: imxfbgrp {
fsl,pins = <
MX27_PAD_LD0__LD0 0x0
MX27_PAD_LD1__LD1 0x0
MX27_PAD_LD2__LD2 0x0
MX27_PAD_LD3__LD3 0x0
MX27_PAD_LD4__LD4 0x0
MX27_PAD_LD5__LD5 0x0
MX27_PAD_LD6__LD6 0x0
MX27_PAD_LD7__LD7 0x0
MX27_PAD_LD8__LD8 0x0
MX27_PAD_LD9__LD9 0x0
MX27_PAD_LD10__LD10 0x0
MX27_PAD_LD11__LD11 0x0
MX27_PAD_LD12__LD12 0x0
MX27_PAD_LD13__LD13 0x0
MX27_PAD_LD14__LD14 0x0
MX27_PAD_LD15__LD15 0x0
MX27_PAD_LD16__LD16 0x0
MX27_PAD_LD17__LD17 0x0
MX27_PAD_CLS__CLS 0x0
MX27_PAD_CONTRAST__CONTRAST 0x0
MX27_PAD_LSCLK__LSCLK 0x0
MX27_PAD_OE_ACD__OE_ACD 0x0
MX27_PAD_PS__PS 0x0
MX27_PAD_REV__REV 0x0
MX27_PAD_SPL_SPR__SPL_SPR 0x0
MX27_PAD_HSYNC__HSYNC 0x0
MX27_PAD_VSYNC__VSYNC 0x0
>;
};
pinctrl_i2c1: i2c1grp {
/* Add pullup to DATA line */
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x1
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_i2c1: i2c1grp {
/* Add pullup to DATA line */
fsl,pins = <
MX27_PAD_I2C_DATA__I2C_DATA 0x1
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
MX27_PAD_USBH2_STP__USBH2_STP 0x0
MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */
MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */
MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
>;
};
};

154
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
View File

@ -192,90 +192,88 @@ lm75@4a {
};
&iomuxc {
imx27_phycore_som {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
>;
};
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI1_FS__SSI1_FS 0x0
MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
>;
};
pinctrl_ssi1: ssi1grp {
fsl,pins = <
MX27_PAD_SSI1_FS__SSI1_FS 0x0
MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
>;
};
};

4
arch/arm/boot/dts/nxp/imx/imx27.dtsi
View File

@ -49,7 +49,7 @@ aitc: aitc-interrupt-controller@10040000 {
clocks {
clk_osc26m: osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
@ -289,7 +289,7 @@ sdhci2: mmc@10014000 {
status = "disabled";
};
iomuxc: iomuxc@10015000 {
iomuxc: pinmux@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;

2
arch/arm/boot/dts/nxp/imx/imx31.dtsi
View File

@ -333,7 +333,7 @@ pwm: pwm@53fe0000 {
};
};
emi@b8000000 { /* External Memory Interface */
emi-bus@b8000000 { /* External Memory Interface */
compatible = "simple-bus";
reg = <0xb8000000 0x5000>;
ranges;

30
arch/arm/boot/dts/nxp/imx/imx35.dtsi
View File

@ -79,7 +79,7 @@ i2c1: i2c@43f80000 {
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f80000 0x4000>;
clocks = <&clks 51>;
clock-names = "ipg_per";
clock-names = "ipg";
interrupts = <10>;
status = "disabled";
};
@ -90,7 +90,7 @@ i2c3: i2c@43f84000 {
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f84000 0x4000>;
clocks = <&clks 53>;
clock-names = "ipg_per";
clock-names = "ipg";
interrupts = <3>;
status = "disabled";
};
@ -119,7 +119,7 @@ i2c2: i2c@43f98000 {
compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
reg = <0x43f98000 0x4000>;
clocks = <&clks 52>;
clock-names = "ipg_per";
clock-names = "ipg";
interrupts = <4>;
status = "disabled";
};
@ -356,7 +356,7 @@ usbmisc: usbmisc@53ff4600 {
};
};
emi@80000000 { /* External Memory Interface */
emi-bus@80000000 { /* External Memory Interface */
compatible = "fsl,emi", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -393,21 +393,13 @@ weim: memory-controller@b8002000 {
};
};
usbphy {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usbphy0: usb-phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
usbphy0: usb-phy@0 {
reg = <0>;
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
usbphy1: usb-phy@1 {
reg = <1>;
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
usbphy1: usb-phy1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
View File

@ -327,7 +327,7 @@ vgen3_reg: vgen3 {
};
};
flash: at45db321d@1 {
flash: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";

2
arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
View File

@ -141,7 +141,7 @@ &weim {
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
fpga@0 {
fpga-bus@0,0 {
compatible = "simple-bus";
fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
0x00000000 0x1c092480 0x00000000>;

18
arch/arm/boot/dts/nxp/imx/imx53-smd.dts
View File

@ -31,6 +31,20 @@ key-volume-down {
linux,code = <KEY_VOLUMEDOWN>;
};
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&esdhc1 {
@ -253,6 +267,10 @@ &i2c2 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clks IMX5_CLK_DUMMY>;
VDDA-supply = <&reg_1v8>;
VDDIO-supply = <&reg_3v3>;
};
magnetometer: mag3110@e {

4
arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts
View File

@ -193,8 +193,8 @@ &can1 {
};
&clks {
clocks = <&clock_ksz8081>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clock_ksz8081>;
};

4
arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts
View File

@ -66,8 +66,8 @@ &can2 {
};
&clks {
clocks = <&rmii_clk>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&rmii_clk>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&rmii_clk>;
};

4
arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts
View File

@ -119,8 +119,8 @@ &can2 {
};
&clks {
clocks = <&clock_ksz8081>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clock_ksz8081>;
};

4
arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts
View File

@ -101,8 +101,8 @@ &can2 {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clk50m_phy>;
};

4
arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts
View File

@ -199,8 +199,8 @@ &can1 {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clk50m_phy>;
};

4
arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts
View File

@ -294,8 +294,8 @@ &can2 {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
};

5
arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi
View File

@ -71,8 +71,9 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
};
&clks {
clocks = <&rtc_sqw>;
clock-names = "ckil";
clocks = <&osc>, <&rtc_sqw>, <&ckih1>, <&anaclk1>, <&anaclk2>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2";
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,

4
arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts
View File

@ -160,8 +160,8 @@ vdiv_hitch_pos: voltage-divider-hitch-pos {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clk50m_phy>;
};

1
arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
View File

@ -140,6 +140,7 @@ port@3 {
port@4 {
reg = <4>;
label = "cpu";
phy-mode = "gmii";
ethernet = <&switch_nic>;
phy-handle = <&switchphy4>;
};

1
arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
View File

@ -139,6 +139,7 @@ port@3 {
port@4 {
reg = <4>;
label = "cpu";
phy-mode = "gmii";
ethernet = <&switch_nic>;
phy-handle = <&switchphy4>;
};

53
arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
View File

@ -53,23 +53,20 @@ chosen {
};
};
&ldb {
fsl,dual-channel;
status = "okay";
&gpio4 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "PWGIN", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&stdp4028_in>;
};
};
};
&hdmi {
ddc-i2c-bus = <&mux2_i2c1>;
};
&i2c2 {
@ -129,8 +126,23 @@ mux2_i2c8: i2c@7 {
};
};
&hdmi {
ddc-i2c-bus = <&mux2_i2c1>;
&ldb {
fsl,dual-channel;
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&stdp4028_in>;
};
};
};
};
&mux1_i2c1 {
@ -286,7 +298,12 @@ port@3 {
port@4 {
reg = <4>;
label = "cpu";
phy-mode = "gmii";
ethernet = <&switch_nic>;
phy-handle = <&switchphy4>;
};
};
&usdhc4 {
status = "disabled";
};

4
arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
View File

@ -124,24 +124,28 @@ switchphy0: switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
max-speed = <100>; /* only 100Mbit/s lanes are routed */
};
switchphy1: switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
max-speed = <100>; /* only 100Mbit/s lanes are routed */
};
switchphy2: switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
max-speed = <100>; /* only 100Mbit/s lanes are routed */
};
switchphy3: switchphy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
max-speed = <100>; /* only 100Mbit/s lanes are routed */
};
switchphy4: switchphy@4 {

4
arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts
View File

@ -57,8 +57,8 @@ &can1 {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clk50m_phy>;
};

75
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi Normal file
View File

@ -0,0 +1,75 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi"
&{/} {
lvds-encoder {
compatible = "onnn,fin3385", "lvds-encoder";
pclk-sample = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_bridge_in: endpoint {
remote-endpoint = <&ipu1_dpi0_out>;
};
};
port@1 {
reg = <1>;
lvds_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
&display_bl {
pwms = <&pwm1 0 5000000 0>;
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
interrupt-parent = <&gpio4>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <16384>;
touchscreen-size-y = <9600>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&ipu1_dpi0_out {
remote-endpoint = <&lvds_bridge_in>;
};
&panel {
compatible = "chefree,ch101olhlwh-002";
};
&panel_in {
remote-endpoint = <&lvds_bridge_out>;
};

61
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi.dtsi Normal file
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pwm/pwm.h>
&{/} {
display_bl: display-bl {
compatible = "pwm-backlight";
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <8>;
enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
lcd_display: disp0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_lcdif>;
status = "okay";
port@0 {
reg = <0>;
ipu1_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
ipu1_dpi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel: panel {
backlight = <&display_bl>;
port {
panel_in: endpoint {
};
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&ipu1_display_in>;
};
&pwm1 {
status = "okay";
};

28
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtso Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi"
&display_bl {
pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
};
&ipu1_dpi0_out {
remote-endpoint = <&panel_in>;
};
&panel {
compatible = "dataimage,scf0700c48ggu18";
};
&panel_in {
remote-endpoint = <&ipu1_dpi0_out>;
};
&touch_som { /* TSC2004 */
status = "okay";
};

26
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi"
&{/} {
gpio-keys {
/* BUTTON1 GPIO-B conflicts with touchscreen reset */
button-1 {
/* Use status as /delete-node/ does not work in DTOs */
status = "disabled";
};
};
led {
/* LED7 GPIO-H conflicts with touchscreen IRQ */
led-7 {
/* Use status as /delete-node/ does not work in DTOs */
status = "disabled";
};
};
};

32
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtso Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@1 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <1>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

32
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtso Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
eeprom@0 {
compatible = "microchip,25aa010a", "atmel,at25";
reg = <0>;
address-width = <8>;
pagesize = <16>;
size = <128>;
spi-max-frequency = <5000000>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@56 {
compatible = "atmel,24c04";
reg = <0x56>;
pagesize = <16>;
};
};

39
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtso Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2021-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi"
&display_bl {
pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dhcom_e>;
/* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
};
};
&ipu1_dpi0_out {
remote-endpoint = <&panel_in>;
};
&panel {
compatible = "edt,etm0700g0edh6";
};
&panel_in {
remote-endpoint = <&ipu1_dpi0_out>;
};

8
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023-2026 Marek Vasut
*/
/dts-v1/;
/plugin/;
#include "imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi"

6
arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2021 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
* Copyright (C) 2015-2026 DH electronics GmbH
* Copyright (C) 2018-2026 Marek Vasut
*/
#include <dt-bindings/pwm/pwm.h>
@ -303,7 +303,7 @@ ldo2_reg: ldo2 {
};
};
touchscreen@49 { /* TSC2004 */
touch_som: touchscreen@49 { /* TSC2004 */
compatible = "ti,tsc2004";
interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_tsc2004>;

12
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi
View File

@ -206,6 +206,10 @@ ethphy: ethernet-phy@3 {
};
};
&gpio1 {
bootph-pre-ram;
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
@ -214,6 +218,8 @@ &hdmi {
};
&i2c1 {
bootph-pre-ram;
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
@ -274,6 +280,7 @@ &ssi1 {
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
bootph-pre-ram;
status = "okay";
};
@ -346,6 +353,7 @@ &usdhc2 {
no-sdio;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
bootph-all;
status = "okay";
};
@ -354,6 +362,7 @@ &wdog1 {
pinctrl-0 = <&pinctrl_wdog1>;
/* does not work on unmodified starter kit */
/* fsl,ext-reset-output; */
bootph-pre-ram;
status = "okay";
};
@ -544,6 +553,7 @@ pinctrl_uart2: uart2grp {
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
bootph-pre-ram;
};
pinctrl_uart3: uart3grp {
@ -587,6 +597,7 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
bootph-all;
};
pinctrl_usbotg: usbotggrp {
@ -602,5 +613,6 @@ pinctrl_wdog1: wdog1grp {
/* Watchdog out */
MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
>;
bootph-pre-ram;
};
};

4
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -238,8 +238,8 @@ adc: adc@0 {
};
&clks {
clocks = <&clk50m_phy>;
clock-names = "enet_ref_pad";
clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>;
clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
assigned-clock-parents = <&clk50m_phy>;
};

8
arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi
View File

@ -41,6 +41,12 @@
#include <dt-bindings/gpio/gpio.h>
/ {
clk32k: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
nvcc_sd1: regulator-nvcc-sd1 {
compatible = "regulator-fixed";
regulator-always-on;
@ -58,7 +64,7 @@ clk_ti_wifi: ti-wifi-clock {
*/
compatible = "gpio-gate-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clocks = <&clk32k>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_ti_clk>;
enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;

11
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi
View File

@ -11,6 +11,7 @@ &ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
bootph-pre-ram;
status = "okay";
m25p80: flash@0 {
@ -19,6 +20,7 @@ m25p80: flash@0 {
spi-max-frequency = <50000000>;
vcc-supply = <&sw4_reg>;
m25p,fast-read;
bootph-pre-ram;
partitions {
compatible = "fixed-partitions";
@ -28,6 +30,10 @@ partitions {
};
};
&gpio3 {
bootph-pre-ram;
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
@ -38,6 +44,7 @@ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
bootph-pre-ram;
};
pinctrl_i2c1: i2c1grp {
@ -45,6 +52,7 @@ pinctrl_i2c1: i2c1grp {
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
bootph-pre-ram;
};
pinctrl_i2c1_recovery: i2c1recoverygrp {
@ -73,6 +81,7 @@ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
bootph-all;
};
};
@ -117,6 +126,7 @@ sw4_reg: sw4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
bootph-pre-ram;
};
reg_5v_600mA: swbst {
@ -186,6 +196,7 @@ &usdhc3 {
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;
bootph-all;
status = "okay";
mmccard: mmccard@0 {

5
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi
View File

@ -20,6 +20,7 @@ &i2c1 {
scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
bootph-pre-ram;
status = "okay";
pmic: pmic@8 {
@ -27,13 +28,13 @@ pmic: pmic@8 {
reg = <0x08>;
};
temperature-sensor@48 {
lm75_48: temperature-sensor@48 {
compatible = "national,lm75a";
reg = <0x48>;
vs-supply = <&sw4_reg>;
};
eeprom@50 {
m24c64_50: eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;

6
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi
View File

@ -13,6 +13,7 @@ &i2c3 {
scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
bootph-pre-ram;
status = "okay";
pmic: pmic@8 {
@ -20,13 +21,13 @@ pmic: pmic@8 {
reg = <0x08>;
};
temperature-sensor@48 {
lm75_48: temperature-sensor@48 {
compatible = "national,lm75a";
reg = <0x48>;
vs-supply = <&sw4_reg>;
};
eeprom@50 {
m24c64_50: eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
@ -40,6 +41,7 @@ pinctrl_i2c3: i2c3grp {
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
bootph-pre-ram;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {

24
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
View File

@ -54,23 +54,35 @@ aliases {
};
clocks {
ckil {
ckil: ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
ckih1: ckih1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
osc: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
anaclk1: anaclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
anaclk2: anaclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};
ldb: ldb {
@ -149,6 +161,7 @@ soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
bootph-all;
dma_apbh: dma-controller@110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@ -297,6 +310,7 @@ aips1: bus@2000000 { /* AIPS1 */
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
bootph-pre-ram;
spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -304,6 +318,7 @@ spba-bus@2000000 {
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
bootph-pre-ram;
spdif: spdif@2004000 {
compatible = "fsl,imx35-spdif";
@ -920,6 +935,7 @@ mux: mux-controller {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x20e0000 0x4000>;
bootph-pre-ram;
};
dcic1: dcic@20e4000 {
@ -950,6 +966,7 @@ aips2: bus@2100000 { /* AIPS2 */
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
bootph-pre-ram;
crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
@ -1320,6 +1337,7 @@ ipu1: ipu@2400000 {
<&clks IMX6QDL_CLK_IPU1_DI1>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
bootph-all;
ipu1_csi0: port@0 {
reg = <0>;

4
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View File

@ -1304,7 +1304,7 @@ csi2: csi@221c000 {
};
lcdif1: lcdif@2220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
compatible = "fsl,imx6sx-lcdif";
reg = <0x02220000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
@ -1325,7 +1325,7 @@ lcdif1_to_ldb: endpoint {
};
lcdif2: lcdif@2224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
compatible = "fsl,imx6sx-lcdif";
reg = <0x02224000 0x4000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,

10
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
View File

@ -26,6 +26,7 @@ &i2c4 {
pinctrl-1 = <&pinctrl_i2c4_recovery>;
scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
bootph-pre-ram;
status = "okay";
pfuze3000: pmic@8 {
@ -140,9 +141,14 @@ rtc0: rtc@68 {
};
};
&gpio1 {
bootph-pre-ram;
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
bootph-pre-ram;
/*
* PMIC & temperature sensor IRQ
@ -159,6 +165,7 @@ pmic-int-hog {
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
bootph-pre-ram;
status = "okay";
flash0: flash@0 {
@ -168,6 +175,7 @@ flash0: flash@0 {
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&reg_vldo4>;
bootph-pre-ram;
partitions {
compatible = "fixed-partitions";
@ -189,6 +197,7 @@ &usdhc2 {
non-removable;
no-sdio;
no-sd;
bootph-all;
status = "okay";
};
@ -212,5 +221,6 @@ pinctrl_pmic: pmicgrp {
/* PMIC irq */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099
>;
bootph-pre-ram;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi
View File

@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

4
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright 2018-2022 TQ Systems GmbH
* Copyright 2018-2022 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
@ -10,6 +10,6 @@
#include "mba6ulx.dtsi"
/ {
model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
model = "TQ-Systems TQMa6UL2L SoM on MBa6ULx board";
compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi
View File

@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi
View File

@ -39,5 +39,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
bootph-pre-ram;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi
View File

@ -44,5 +44,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
bootph-pre-ram;
};
};

7
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
View File

@ -115,6 +115,7 @@ osc: clock-osc {
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
bootph-pre-ram;
};
ipp_di0: clock-di0 {
@ -143,6 +144,7 @@ soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
bootph-pre-ram;
ocram: sram@900000 {
compatible = "mmio-sram";
@ -202,6 +204,7 @@ aips1: bus@2000000 {
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
bootph-pre-ram;
spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -209,6 +212,7 @@ spba-bus@2000000 {
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
bootph-pre-ram;
ecspi1: spi@2008000 {
#address-cells = <1>;
@ -580,6 +584,7 @@ clks: clock-controller@20c4000 {
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
bootph-pre-ram;
};
anatop: anatop@20c8000 {
@ -745,6 +750,7 @@ power-domain@0 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
bootph-pre-ram;
};
gpr: iomuxc-gpr@20e4000 {
@ -826,6 +832,7 @@ aips2: bus@2100000 {
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
bootph-pre-ram;
crypto: crypto@2140000 {
compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";

4
arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi
View File

@ -201,7 +201,7 @@ &uart2 {
* the speed can be increased accordingly.
*/
bluetooth: bluetooth {
compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */
compatible = "brcm,bcm4329-bt"; /* muRata 1DX or 1YN */
max-speed = <3000000>;
vbat-supply = <&vcc_3v3>;
vddio-supply = <&vcc_3v3>;
@ -222,7 +222,7 @@ &usdhc1 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */
compatible = "brcm,bcm4329-fmac"; /* muRata 1DX or 1YN */
reg = <1>;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts
View File

@ -154,6 +154,7 @@ &tsc {
pinctrl-0 = <&pinctrl_tsc>;
measure-delay-time = <0x9ffff>;
pre-charge-time = <0xfff>;
debounce-delay-us = <62>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi
View File

@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

2
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts
View File

@ -10,6 +10,6 @@
#include "mba6ulx.dtsi"
/ {
model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board";
model = "TQ-Systems TQMa6ULL2L SoM on MBa6ULx board";
compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
};

3
arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi
View File

@ -9,7 +9,7 @@
#include "imx6ul-tqma6ulxl-common.dtsi"
/ {
model = "TQ Systems TQMa6ULL2L SoM";
model = "TQ-Systems TQMa6ULL2L SoM";
compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
};
@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
/* rst */
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
>;
bootph-all;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

1
arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
View File

@ -57,6 +57,7 @@ aips3: bus@2200000 {
#size-cells = <1>;
reg = <0x02200000 0x100000>;
ranges;
bootph-pre-ram;
dcp: crypto@2280000 {
compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";

13
arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
View File

@ -287,6 +287,15 @@ &flexcan2 {
status = "okay";
};
&gpio4 {
/* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */
boot-en-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
};
};
&i2c1 {
lm75: temperature-sensor@49 {
compatible = "national,lm75a";
@ -477,6 +486,7 @@ pinctrl_uart5: uart5grp {
};
pinctrl_uart6: uart6grp {
bootph-pre-ram;
fsl,pins =
<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>,
<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>,
@ -511,6 +521,7 @@ pinctrl_usdhc1: usdhc1grp {
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>;
bootph-pre-ram;
};
pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
@ -602,6 +613,7 @@ &uart6 {
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
bootph-pre-ram;
status = "okay";
};
@ -646,6 +658,7 @@ &usdhc1 {
no-1-8-v;
no-sdio;
no-mmc;
bootph-pre-ram;
status = "okay";
};

5
arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi
View File

@ -193,6 +193,7 @@ pinctrl_qspi: qspigrp {
<MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>,
<MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>,
<MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>;
bootph-pre-ram;
};
pinctrl_qspi_reset: qspi_resetgrp {
@ -214,6 +215,7 @@ pinctrl_usdhc3: usdhc3grp {
<MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>,
<MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>,
<MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>;
bootph-pre-ram;
};
pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp {
@ -257,6 +259,7 @@ pinctrl_wdog1: wdog1grp {
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
bootph-pre-ram;
status = "okay";
flash0: flash@0 {
@ -266,6 +269,7 @@ flash0: flash@0 {
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
vcc-supply = <&vgen4_reg>;
bootph-pre-ram;
partitions {
compatible = "fixed-partitions";
@ -288,6 +292,7 @@ &usdhc3 {
no-sdio;
vmmc-supply = <&vgen4_reg>;
vqmmc-supply = <&sw2_reg>;
bootph-pre-ram;
status = "okay";
};

2
arch/arm/boot/dts/nxp/imx/imx7s-warp.dts
View File

@ -199,8 +199,6 @@ ov2680: camera@36 {
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
clock-lanes = <0>;
data-lanes = <1>;
link-frequencies = /bits/ 64 <330000000>;
};
};

5
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
View File

@ -209,6 +209,7 @@ soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
bootph-pre-ram;
ocram: sram@900000 {
compatible = "mmio-sram";
@ -371,6 +372,7 @@ aips1: bus@30000000 {
#size-cells = <1>;
reg = <0x30000000 0x400000>;
ranges;
bootph-pre-ram;
gpio1: gpio@30200000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
@ -543,6 +545,7 @@ kpp: keypad@30320000 {
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
bootph-pre-ram;
};
gpr: iomuxc-gpr@30340000 {
@ -712,6 +715,7 @@ aips2: bus@30400000 {
#size-cells = <1>;
reg = <0x30400000 0x400000>;
ranges;
bootph-pre-ram;
adc1: adc@30610000 {
compatible = "fsl,imx7d-adc";
@ -902,6 +906,7 @@ aips3: bus@30800000 {
#size-cells = <1>;
reg = <0x30800000 0x400000>;
ranges;
bootph-pre-ram;
spba-bus@30800000 {
compatible = "fsl,spba-bus", "simple-bus";

28
arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
View File

@ -41,6 +41,34 @@ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <&smc1 IMX7ULP_CLK_ARM>,
<&scg1 IMX7ULP_CLK_CORE>,
<&scg1 IMX7ULP_CLK_SYS_SEL>,
<&scg1 IMX7ULP_CLK_HSRUN_CORE>,
<&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>,
<&scg1 IMX7ULP_CLK_FIRC>;
clock-names = "arm", "core", "scs_sel",
"hsrun_core", "hsrun_scs_sel",
"firc";
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-500210000 {
opp-hz = /bits/ 64 <500210000>;
opp-microvolt = <1025000>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1125000>;
clock-latency-ns = <150000>;
};
};

6
arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
View File

@ -95,6 +95,7 @@ reg_mba6ul_3v3: regulator-mba6ul-3v3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
bootph-pre-ram;
};
reg_mba6ul_5v0: regulator-mba6ul-5v0 {
@ -336,6 +337,7 @@ &sai1 {
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
bootph-pre-ram;
status = "okay";
};
@ -392,6 +394,7 @@ &usdhc1 {
no-1-8-v;
no-mmc;
no-sdio;
bootph-all;
status = "okay";
};
@ -399,6 +402,7 @@ &wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
fsl,ext-reset-output;
bootph-pre-ram;
status = "okay";
};
@ -494,6 +498,7 @@ pinctrl_uart1: uart1grp {
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
bootph-pre-ram;
};
pinctrl_uart3: uart3grp {
@ -542,6 +547,7 @@ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
/* CD */
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
>;
bootph-all;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {

2
arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts
View File

@ -116,7 +116,7 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio2_1>;
user {
led-user {
label = "green";
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
};

6
arch/arm/boot/dts/nxp/mxs/imx23.dtsi
View File

@ -420,9 +420,9 @@ dma_apbx: dma-controller@80024000 {
<60>, <58>, <9>, <0>,
<0>, <0>, <0>, <0>;
interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
"saif0", "empty", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty",
"empty", "empty", "empty", "empty";
"saif0", "empty0", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty1",
"empty2", "empty3", "empty4", "empty5";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 16>;

2
arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts
View File

@ -29,7 +29,7 @@ reg_can0_vcc: regulator-1 {
leds {
compatible = "gpio-leds";
user {
led-user {
label = "Heartbeat";
gpios = <&gpio0 21 0>;
linux,default-trigger = "heartbeat";

2
arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts
View File

@ -31,7 +31,7 @@ sound {
leds {
compatible = "gpio-leds";
user {
led-user {
label = "Heartbeat";
gpios = <&gpio3 28 0>;
linux,default-trigger = "heartbeat";

2
arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts
View File

@ -21,7 +21,7 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins_cfa10036>;
power {
led-power {
gpios = <&gpio3 4 1>;
default-state = "on";
};

2
arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts
View File

@ -107,7 +107,7 @@ hx8357: hx8357@0 {
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
gpios-reset = <&gpio3 30 0>;
reset-gpios = <&gpio3 30 0>;
im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>;
};
};

2
arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts
View File

@ -33,7 +33,7 @@ hx8357: hx8357@0 {
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
gpios-reset = <&gpio3 30 0>;
reset-gpios = <&gpio3 30 0>;
};
};

2
arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts
View File

@ -32,7 +32,7 @@ hx8369: hx8369@0 {
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
gpios-reset = <&gpio3 30 0>;
reset-gpios = <&gpio3 30 0>;
};
};
};

4
arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts
View File

@ -12,12 +12,12 @@ / {
compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
leds {
rs485-red {
led-rs485-red {
label = "duckbill:red:rs485";
gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
};
rs485-green {
led-rs485-green {
label = "duckbill:green:rs485";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
};

6
arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts
View File

@ -13,17 +13,17 @@ / {
compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
leds {
enocean-blue {
led-enocean-blue {
label = "duckbill:blue:enocean";
gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
};
enocean-red {
led-enocean-red {
label = "duckbill:red:enocean";
gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
};
enocean-green {
led-enocean-green {
label = "duckbill:green:enocean";
gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
};

4
arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts
View File

@ -31,13 +31,13 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
status-red {
led-status-red {
label = "duckbill:red:status";
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
status-green {
led-status-green {
label = "duckbill:green:status";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";

4
arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts
View File

@ -30,13 +30,13 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
status-red {
led-status-red {
label = "duckbill:red:status";
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
status-green {
led-status-green {
label = "duckbill:green:status";
gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";

2
arch/arm/boot/dts/nxp/mxs/imx28-evk.dts
View File

@ -108,7 +108,7 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio3_5>;
user {
led-user {
label = "Heartbeat";
gpios = <&gpio3 5 0>;
linux,default-trigger = "heartbeat";

4
arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts
View File

@ -27,13 +27,13 @@ leds {
pinctrl-names = "default";
pinctrl-0 = <&led_pins_gpio>;
user1 {
led-user1 {
label = "sd0-led";
gpios = <&gpio2 26 0>;
linux,default-trigger = "mmc0";
};
user2 {
led-user2 {
label = "sd1-led";
gpios = <&gpio2 24 0>;
linux,default-trigger = "mmc2";

2
arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts
View File

@ -127,7 +127,7 @@ &ssp2 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "everspin,mr25h256", "mr25h256";
compatible = "everspin,mr25h256";
spi-max-frequency = <40000000>;
reg = <0>;
};

9
arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts
View File

@ -20,11 +20,6 @@ aliases {
ds1339 = &ds1339;
gpio5 = &gpio5;
lcdif = &lcdif;
lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
lcdif_24bit_pins = &lcdif_24bit_pins_a;
reg_can_xcvr = &reg_can_xcvr;
spi_gpio = &spi_gpio;
spi_mxs = &ssp3;
stk5led = &user_led;
usbotg = &usb0;
};
@ -122,7 +117,7 @@ sound {
leds {
compatible = "gpio-leds";
user_led: user {
user_led: led-user {
label = "Heartbeat";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@ -280,7 +275,7 @@ gpio5: pca953x@20 {
};
polytouch: edt-ft5x06@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&tx28_edt_ft5x06_pins>;