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KVM: arm64: Add KVM_PGTABLE_S2_AS_S1 flag

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Plumb the MT_S2{,_FWB}_AS_S1 memory types into the KVM_S2_MEMATTR()
macro with a new KVM_PGTABLE_S2_AS_S1 flag.

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Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260123191637.715429-3-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier 2026-01-23 19:16:34 +00:00
parent d4236f1ef2
commit 17d7b15131
2 changed files with 15 additions and 1 deletions
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2
arch/arm64/include/asm/kvm_pgtable.h
View File

@ -232,10 +232,12 @@ struct kvm_pgtable_mm_ops {
* @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have
* ARM64_HAS_STAGE2_FWB.
* @KVM_PGTABLE_S2_IDMAP: Only use identity mappings.
* @KVM_PGTABLE_S2_AS_S1: Final memory attributes are that of Stage-1.
*/
enum kvm_pgtable_stage2_flags {
KVM_PGTABLE_S2_NOFWB = BIT(0),
KVM_PGTABLE_S2_IDMAP = BIT(1),
KVM_PGTABLE_S2_AS_S1 = BIT(2),
};
/**

14
arch/arm64/kvm/hyp/pgtable.c
View File

@ -659,7 +659,19 @@ void kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,
}
}
#define KVM_S2_MEMATTR(pgt, attr) PAGE_S2_MEMATTR(attr, stage2_has_fwb(pgt))
#define KVM_S2_MEMATTR(pgt, attr) \
({ \
kvm_pte_t __attr; \
\
if ((pgt)->flags & KVM_PGTABLE_S2_AS_S1) \
__attr = PAGE_S2_MEMATTR(AS_S1, \
stage2_has_fwb(pgt)); \
else \
__attr = PAGE_S2_MEMATTR(attr, \
stage2_has_fwb(pgt)); \
\
__attr; \
})
static int stage2_set_xn_attr(enum kvm_pgtable_prot prot, kvm_pte_t *attr)
{