mirror of
https://github.com/torvalds/linux.git
synced 2026-05-29 17:43:52 +02:00
i.MX clock drivers update for 5.7:
- A series from Anson to convert i.MX8 clock bindings to json-schema.
- Update pll14xx driver to include new frequency entries for pll1443x
table, and return error for invalid PLL type.
- Clean up header includes and unnecessary code on a few clock driver.
- Add mssing of_node_put() call for a number of clock drivers.
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock.
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need to
change ARM PLL frequency. Thus, we can support core running above
1GHz safely.
- Update pfdv2 driver to check zero rate and use determine_rate for
getting the best rate.
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5vHoUUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM6lNgf/Qe1jojmzjLPD/QhC31sDrQMTZ+vQ
K309EiXjcZdJ8QTIRTO9IIPHYzy82vjCNywzdy1azQEmPAqDj+MPAjRLu3KLFjr5
husU0wzSdGvkPQ7d4w+GI/4KfeP0evyXFioGyMKF//iFUKrurSc08ZbMBNtLsrQu
a6iTia2+1UDzKbN5grKNu/JKYdAceoca1fRNCvkoysKUnqOm9be5eT0QfA7v+V8A
I8qhGjKAzI8R2cfxuxRAG9Zw3/b2nbvzngkRMauId7nkD+gYTcP4q9la1ZibbR68
K6lZqjpi5BTN+5cDxkI3ezEstGshVJvd5jDeh2IIzcFCdeG5JF/pUsbZ+A==
=h3BT
-----END PGP SIGNATURE-----
Merge tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver updates from Shawn Guo:
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update pll14xx driver to include new frequency entries for pll1443x
table, and return error for invalid PLL type
- Clean up header includes and unnecessary code on a few clock driver
- Add mssing of_node_put() call for a number of clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need to
change ARM PLL frequency. Thus, we can support core running above
1GHz safely
- Update pfdv2 driver to check zero rate and use determine_rate for
getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d
* tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
clk: imx: clk-gate2: Pass the device to the register function
clk: imx7d: Add PXP clock
clk: imx8mq: A53 core clock no need to be critical
clk: imx8mp: A53 core clock no need to be critical
clk: imx8mm: A53 core clock no need to be critical
clk: imx8mn: A53 core clock no need to be critical
clk: imx: pllv4: use prepare/unprepare
clk: imx: pfdv2: determine best parent rate
clk: imx: pfdv2: switch to use determine_rate
clk: imx: Fix division by zero warning on pfdv2
clk: imx: clk-sscg-pll: Drop unnecessary initialization
clk: imx: pll14xx: Return error if pll type is invalid
clk: imx: imx8mp: fix a53 cpu clock
clk: imx: imx8mn: fix a53 cpu clock
clk: imx: imx8mm: fix a53 cpu clock
clk: imx: imx8mq: fix a53 cpu clock
clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock
clk: imx8mn: Remove unused includes
clk: imx8mm: Remove unused includes
clk: imx8mp: Include slab.h instead of clkdev.h
...
This commit is contained in:
Stephen Boyd
commit
17bbcd7d5f
|
|
@ -1,29 +0,0 @@
|
|||
* Clock bindings for NXP i.MX8M Mini
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mm-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "osc_32k"
|
||||
- "osc_24m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
68
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
Normal file
68
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/imx8mm-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Mini Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Mini clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mm-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_32k
|
||||
- const: osc_24m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -40,7 +40,7 @@ properties:
|
|||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
|
||||
for the full list of i.MX8M Nano clock IDs.
|
||||
|
|
@ -57,7 +57,7 @@ examples:
|
|||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mn-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
|
||||
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
|
||||
|
|
@ -65,48 +65,4 @@ examples:
|
|||
"clk_ext2", "clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
# Required external clocks for Clock Control Module node:
|
||||
- |
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
* Clock bindings for NXP i.MX8M Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mq-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "ckil"
|
||||
- "osc_25m"
|
||||
- "osc_27m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
72
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
Normal file
72
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/imx8mq-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Quad Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Quad clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mq-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 25m osc
|
||||
- description: 27m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc_25m
|
||||
- const: osc_27m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
||||
<&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "ckil", "osc_25m", "osc_27m",
|
||||
"clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -15,6 +15,7 @@
|
|||
#define PCG_PREDIV_MAX 8
|
||||
|
||||
#define PCG_DIV_SHIFT 0
|
||||
#define PCG_CORE_DIV_WIDTH 3
|
||||
#define PCG_DIV_WIDTH 6
|
||||
#define PCG_DIV_MAX 64
|
||||
|
||||
|
|
@ -91,7 +92,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
|
|||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
int prediv_value;
|
||||
int div_value;
|
||||
int ret;
|
||||
|
|
@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
|
|||
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
||||
const char * const *parent_names,
|
||||
int num_parents, void __iomem *reg,
|
||||
u32 composite_flags,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
|
||||
|
|
@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
struct clk_divider *div = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_mux *mux = NULL;
|
||||
const struct clk_ops *divider_ops;
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
|
|
@ -150,8 +153,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
|
||||
div_hw = &div->hw;
|
||||
div->reg = reg;
|
||||
div->shift = PCG_PREDIV_SHIFT;
|
||||
div->width = PCG_PREDIV_WIDTH;
|
||||
if (composite_flags & IMX_COMPOSITE_CORE) {
|
||||
div->shift = PCG_DIV_SHIFT;
|
||||
div->width = PCG_CORE_DIV_WIDTH;
|
||||
divider_ops = &clk_divider_ops;
|
||||
} else {
|
||||
div->shift = PCG_PREDIV_SHIFT;
|
||||
div->width = PCG_PREDIV_WIDTH;
|
||||
divider_ops = &imx8m_clk_composite_divider_ops;
|
||||
}
|
||||
|
||||
div->lock = &imx_ccm_lock;
|
||||
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
|
||||
|
||||
|
|
@ -166,8 +177,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux_hw, &clk_mux_ops, div_hw,
|
||||
&imx8m_clk_composite_divider_ops,
|
||||
gate_hw, &clk_gate_ops, flags);
|
||||
divider_ops, gate_hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(hw))
|
||||
goto fail;
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
unsigned int divider, value;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
divider = parent_rate / rate;
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
{
|
||||
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static int clk_gate2_enable(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
|
|
@ -62,7 +62,7 @@ static void clk_gate2_disable(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
|
|
@ -101,7 +101,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
|
|||
static void clk_gate2_disable_unused(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
|
@ -154,7 +154,7 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
|
|||
gate->hw.init = &init;
|
||||
hw = &gate->hw;
|
||||
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
ret = clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
kfree(gate);
|
||||
return ERR_PTR(ret);
|
||||
|
|
|
|||
|
|
@ -208,6 +208,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
of_node_put(np);
|
||||
anatop_base = base;
|
||||
|
||||
hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
|
|
|||
|
|
@ -802,6 +802,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
hws[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_hw_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
|
||||
hws[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
|
||||
hws[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
|
||||
hws[IMX7D_PXP_CLK] = imx_clk_hw_gate4("pxp_clk", "main_axi_root_clk", base + 0x44c0, 0);
|
||||
hws[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
|
||||
hws[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
|
||||
hws[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_hw_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
|
|
|||
|
|
@ -4,12 +4,10 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mm-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -41,6 +39,8 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
|||
static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
|
||||
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m",
|
||||
"sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
|
||||
|
||||
|
|
@ -283,8 +283,10 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
|
|||
|
||||
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out",
|
||||
"vpu_pll", "sys_pll1_80m", };
|
||||
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
|
||||
"audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
|
||||
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
|
||||
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
|
@ -322,6 +324,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -414,20 +417,30 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* Core Slice */
|
||||
hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
|
||||
hws[IMX8MM_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels));
|
||||
hws[IMX8MM_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base + 0x8100, 24, 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels));
|
||||
hws[IMX8MM_CLK_GPU3D_SRC] = imx_clk_hw_mux2("gpu3d_src", base + 0x8180, 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels));
|
||||
hws[IMX8MM_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src", base + 0x8200, 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels));
|
||||
hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
hws[IMX8MM_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
|
||||
hws[IMX8MM_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
|
||||
hws[IMX8MM_CLK_GPU3D_CG] = imx_clk_hw_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28);
|
||||
hws[IMX8MM_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28);
|
||||
hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MM_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
|
||||
hws[IMX8MM_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
|
||||
hws[IMX8MM_CLK_GPU3D_DIV] = imx_clk_hw_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MM_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
|
||||
hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
|
||||
hws[IMX8MM_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mm_gpu3d_sels, base + 0x8180);
|
||||
hws[IMX8MM_CLK_GPU2D_CORE] = imx8m_clk_hw_composite_core("gpu2d_core", imx8mm_gpu2d_sels, base + 0x8200);
|
||||
|
||||
/* For backwards compatibility */
|
||||
hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_SRC] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_DIV] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_SRC] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_CG] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
|
||||
|
|
@ -504,6 +517,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mm_wdog_sels, base + 0xb900);
|
||||
hws[IMX8MM_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mm_wrclk_sels, base + 0xb980);
|
||||
hws[IMX8MM_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mm_clko1_sels, base + 0xba00);
|
||||
hws[IMX8MM_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mm_clko2_sels, base + 0xba80);
|
||||
hws[IMX8MM_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mm_dsi_core_sels, base + 0xbb00);
|
||||
hws[IMX8MM_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mm_dsi_phy_sels, base + 0xbb80);
|
||||
hws[IMX8MM_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mm_dsi_dbi_sels, base + 0xbc00);
|
||||
|
|
@ -564,7 +578,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
hws[IMX8MM_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
hws[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
hws[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
|
||||
hws[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", base + 0x44f0, 0);
|
||||
hws[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
hws[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
hws[IMX8MM_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
|
|
@ -586,7 +600,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
|
||||
hws[IMX8MM_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
|
||||
hws[IMX8MM_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
hws[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", base + 0x4660, 0);
|
||||
hws[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", base + 0x4660, 0);
|
||||
hws[IMX8MM_CLK_CSI1_ROOT] = imx_clk_hw_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
|
||||
|
||||
hws[IMX8MM_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
|
||||
|
|
@ -594,11 +608,14 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL);
|
||||
|
||||
hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MM_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MM_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MM_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MM_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MM_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MM_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MM_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MM_CLK_END);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,12 +4,10 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -40,6 +38,8 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
|
|||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
|
@ -317,6 +317,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
goto unregister_hws;
|
||||
|
|
@ -413,15 +414,21 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* CORE */
|
||||
hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
|
||||
hws[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
|
||||
hws[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
|
||||
hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
hws[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_hw_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
hws[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
|
||||
hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
|
||||
|
||||
hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
|
||||
|
|
@ -523,12 +530,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
hws[IMX8MN_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
hws[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
|
||||
hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core", base + 0x44f0, 0);
|
||||
hws[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
hws[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
hws[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
|
|
@ -551,11 +559,14 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MN_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MN_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MN_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MN_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MN_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MN_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MN_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC], hws[IMX8MN_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE], hws[IMX8MN_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MN_CLK_END);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
|
@ -34,6 +34,8 @@ static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
|
|||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m",
|
||||
"vpu_pll_out", "sys_pll1_800m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
|
|
@ -342,7 +344,7 @@ static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_26
|
|||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mp_hdmi_27m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
|
|
@ -434,6 +436,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!anatop_base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -553,6 +556,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
|
||||
hws[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3);
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
|
||||
|
||||
hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
|
||||
hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
|
||||
hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
|
||||
|
|
@ -631,7 +637,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00);
|
||||
hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80);
|
||||
hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00);
|
||||
hws[IMX8MP_CLK_HDMI_27M] = imx8m_clk_hw_composite("hdmi_27m", imx8mp_hdmi_27m_sels, ccm_base + 0xbb80);
|
||||
hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80);
|
||||
hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00);
|
||||
hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
|
||||
|
|
@ -671,6 +677,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
|
||||
hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
|
||||
hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
|
||||
hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
|
||||
hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
|
||||
hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
|
||||
hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0);
|
||||
|
|
@ -722,11 +729,14 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
|
||||
hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
|
||||
|
||||
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MP_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MP_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MP_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MP_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MP_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MP_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MP_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], hws[IMX8MP_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], hws[IMX8MP_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MP_CLK_END);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
|
|
@ -41,6 +41,8 @@ static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
|
|||
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
|
|
@ -305,6 +307,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -403,22 +406,29 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* CORE */
|
||||
hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
|
||||
hws[IMX8MQ_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));
|
||||
hws[IMX8MQ_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
|
||||
hws[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels));
|
||||
|
||||
hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
|
||||
hws[IMX8MQ_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
|
||||
hws[IMX8MQ_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
|
||||
hws[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_hw_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MQ_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
|
||||
hws[IMX8MQ_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
|
||||
hws[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
|
||||
hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
|
||||
hws[IMX8MQ_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mq_gpu_core_sels, base + 0x8180);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER] = imx8m_clk_hw_composite("gpu_shader", imx8mq_gpu_shader_sels, base + 0x8200);
|
||||
/* For backwards compatibility */
|
||||
hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_CG] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_DIV] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_SRC] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_CG] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_DIV] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
|
||||
|
|
@ -567,7 +577,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
|
||||
hws[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
|
||||
hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0);
|
||||
hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_core", base + 0x4570, 0);
|
||||
hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX8MQ_CLK_DISP_ROOT] = imx_clk_hw_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
|
||||
hws[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
|
|
@ -583,11 +593,14 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc_25m", 1, 8);
|
||||
hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MQ_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MQ_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MQ_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MQ_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MQ_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MQ_SYS1_PLL_800M]->clk);
|
||||
hws[IMX8MQ_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MQ_CLK_END);
|
||||
|
||||
|
|
|
|||
|
|
@ -98,26 +98,45 @@ static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
|
|||
return tmp;
|
||||
}
|
||||
|
||||
static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
static int clk_pfdv2_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
u64 tmp = *prate;
|
||||
unsigned long parent_rates[] = {
|
||||
480000000,
|
||||
528000000,
|
||||
req->best_parent_rate
|
||||
};
|
||||
unsigned long best_rate = -1UL, rate = req->rate;
|
||||
unsigned long best_parent_rate = req->best_parent_rate;
|
||||
u64 tmp;
|
||||
u8 frac;
|
||||
int i;
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
for (i = 0; i < ARRAY_SIZE(parent_rates); i++) {
|
||||
tmp = parent_rates[i];
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
||||
if (frac < 12)
|
||||
frac = 12;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
if (frac < 12)
|
||||
frac = 12;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
|
||||
tmp = *prate;
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
tmp = parent_rates[i];
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
|
||||
return tmp;
|
||||
if (abs(tmp - req->rate) < abs(best_rate - req->rate)) {
|
||||
best_rate = tmp;
|
||||
best_parent_rate = parent_rates[i];
|
||||
}
|
||||
}
|
||||
|
||||
req->best_parent_rate = best_parent_rate;
|
||||
req->rate = best_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pfdv2_is_enabled(struct clk_hw *hw)
|
||||
|
|
@ -139,6 +158,12 @@ static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
u32 val;
|
||||
u8 frac;
|
||||
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
|
||||
/* PFD can NOT change rate without gating */
|
||||
WARN_ON(clk_pfdv2_is_enabled(hw));
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
|
@ -161,7 +186,7 @@ static const struct clk_ops clk_pfdv2_ops = {
|
|||
.enable = clk_pfdv2_enable,
|
||||
.disable = clk_pfdv2_disable,
|
||||
.recalc_rate = clk_pfdv2_recalc_rate,
|
||||
.round_rate = clk_pfdv2_round_rate,
|
||||
.determine_rate = clk_pfdv2_determine_rate,
|
||||
.set_rate = clk_pfdv2_set_rate,
|
||||
.is_enabled = clk_pfdv2_is_enabled,
|
||||
};
|
||||
|
|
@ -189,7 +214,7 @@ struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
|
|||
init.ops = &clk_pfdv2_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_SET_RATE_GATE;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
|
||||
|
||||
pfd->hw.init = &init;
|
||||
|
||||
|
|
|
|||
|
|
@ -55,8 +55,10 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
|
|||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
|
||||
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
|
@ -408,6 +410,8 @@ struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
|
|||
default:
|
||||
pr_err("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, name);
|
||||
kfree(pll);
|
||||
return ERR_PTR(-EINVAL);
|
||||
};
|
||||
|
||||
pll->base = base;
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
|
|||
csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static int clk_pllv4_is_enabled(struct clk_hw *hw)
|
||||
static int clk_pllv4_is_prepared(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
||||
|
|
@ -175,7 +175,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pllv4_enable(struct clk_hw *hw)
|
||||
static int clk_pllv4_prepare(struct clk_hw *hw)
|
||||
{
|
||||
u32 val;
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
|
@ -187,7 +187,7 @@ static int clk_pllv4_enable(struct clk_hw *hw)
|
|||
return clk_pllv4_wait_lock(pll);
|
||||
}
|
||||
|
||||
static void clk_pllv4_disable(struct clk_hw *hw)
|
||||
static void clk_pllv4_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
u32 val;
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
|
@ -201,9 +201,9 @@ static const struct clk_ops clk_pllv4_ops = {
|
|||
.recalc_rate = clk_pllv4_recalc_rate,
|
||||
.round_rate = clk_pllv4_round_rate,
|
||||
.set_rate = clk_pllv4_set_rate,
|
||||
.enable = clk_pllv4_enable,
|
||||
.disable = clk_pllv4_disable,
|
||||
.is_enabled = clk_pllv4_is_enabled,
|
||||
.prepare = clk_pllv4_prepare,
|
||||
.unprepare = clk_pllv4_unprepare,
|
||||
.is_prepared = clk_pllv4_is_prepared,
|
||||
};
|
||||
|
||||
struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
|
||||
|
|
|
|||
|
|
@ -195,10 +195,10 @@ static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup,
|
|||
uint64_t ref)
|
||||
{
|
||||
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
temp_setup->vco1 = ref;
|
||||
|
||||
|
|
@ -254,10 +254,10 @@ static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup,
|
|||
uint64_t ref)
|
||||
{
|
||||
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
temp_setup->ref = ref;
|
||||
|
||||
|
|
@ -428,7 +428,7 @@ static int __clk_sscg_pll_determine_rate(struct clk_hw *hw,
|
|||
struct clk_sscg_pll_setup *setup = &pll->setup;
|
||||
struct clk_hw *parent_hw = NULL;
|
||||
int bypass_parent_index;
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
req->max_rate = max;
|
||||
req->min_rate = min;
|
||||
|
|
@ -467,10 +467,10 @@ static int clk_sscg_pll_determine_rate(struct clk_hw *hw,
|
|||
uint64_t rate = req->rate;
|
||||
uint64_t min = req->min_rate;
|
||||
uint64_t max = req->max_rate;
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
ret = __clk_sscg_pll_determine_rate(hw, req, req->rate, req->rate,
|
||||
rate, PLL_BYPASS2);
|
||||
|
|
|
|||
|
|
@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
|
|||
struct clk *div, struct clk *mux, struct clk *pll,
|
||||
struct clk *step);
|
||||
|
||||
#define IMX_COMPOSITE_CORE BIT(0)
|
||||
|
||||
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
||||
const char * const *parent_names,
|
||||
int num_parents,
|
||||
void __iomem *reg,
|
||||
u32 composite_flags,
|
||||
unsigned long flags);
|
||||
|
||||
#define imx8m_clk_hw_composite_core(name, parent_names, reg) \
|
||||
imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
ARRAY_SIZE(parent_names), reg, \
|
||||
IMX_COMPOSITE_CORE, \
|
||||
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||
|
||||
#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
|
||||
flags) \
|
||||
to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
num_parents, reg, flags))
|
||||
num_parents, reg, 0, flags))
|
||||
|
||||
#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
|
||||
imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
ARRAY_SIZE(parent_names), reg, \
|
||||
ARRAY_SIZE(parent_names), reg, 0, \
|
||||
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||
|
||||
#define __imx8m_clk_composite(name, parent_names, reg, flags) \
|
||||
|
|
|
|||
|
|
@ -451,5 +451,6 @@
|
|||
#define IMX7D_SNVS_CLK 442
|
||||
#define IMX7D_CAAM_CLK 443
|
||||
#define IMX7D_KPP_ROOT_CLK 444
|
||||
#define IMX7D_CLK_END 445
|
||||
#define IMX7D_PXP_CLK 445
|
||||
#define IMX7D_CLK_END 446
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
|
|
|||
|
|
@ -265,6 +265,15 @@
|
|||
#define IMX8MM_SYS_PLL2_333M_CG 244
|
||||
#define IMX8MM_SYS_PLL2_500M_CG 245
|
||||
|
||||
#define IMX8MM_CLK_END 246
|
||||
#define IMX8MM_CLK_M4_CORE 246
|
||||
#define IMX8MM_CLK_VPU_CORE 247
|
||||
#define IMX8MM_CLK_GPU3D_CORE 248
|
||||
#define IMX8MM_CLK_GPU2D_CORE 249
|
||||
|
||||
#define IMX8MM_CLK_CLKO2 250
|
||||
|
||||
#define IMX8MM_CLK_A53_CORE 251
|
||||
|
||||
#define IMX8MM_CLK_END 252
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -228,6 +228,12 @@
|
|||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_END 211
|
||||
#define IMX8MN_CLK_SNVS_ROOT 211
|
||||
#define IMX8MN_CLK_GPU_CORE 212
|
||||
#define IMX8MN_CLK_GPU_SHADER 213
|
||||
|
||||
#define IMX8MN_CLK_A53_CORE 214
|
||||
|
||||
#define IMX8MN_CLK_END 215
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -173,7 +173,7 @@
|
|||
#define IMX8MP_CLK_IPP_DO_CLKO1 164
|
||||
#define IMX8MP_CLK_IPP_DO_CLKO2 165
|
||||
#define IMX8MP_CLK_HDMI_FDCC_TST 166
|
||||
#define IMX8MP_CLK_HDMI_27M 167
|
||||
#define IMX8MP_CLK_HDMI_24M 167
|
||||
#define IMX8MP_CLK_HDMI_REF_266M 168
|
||||
#define IMX8MP_CLK_USDHC3 169
|
||||
#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
|
||||
|
|
@ -294,7 +294,8 @@
|
|||
#define IMX8MP_CLK_DRAM_ALT_ROOT 285
|
||||
#define IMX8MP_CLK_DRAM_CORE 286
|
||||
#define IMX8MP_CLK_ARM 287
|
||||
#define IMX8MP_CLK_A53_CORE 288
|
||||
|
||||
#define IMX8MP_CLK_END 288
|
||||
#define IMX8MP_CLK_END 289
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -424,6 +424,13 @@
|
|||
#define IMX8MQ_SYS2_PLL_500M_CG 283
|
||||
#define IMX8MQ_SYS2_PLL_1000M_CG 284
|
||||
|
||||
#define IMX8MQ_CLK_END 285
|
||||
#define IMX8MQ_CLK_GPU_CORE 285
|
||||
#define IMX8MQ_CLK_GPU_SHADER 286
|
||||
#define IMX8MQ_CLK_M4_CORE 287
|
||||
#define IMX8MQ_CLK_VPU_CORE 288
|
||||
|
||||
#define IMX8MQ_CLK_A53_CORE 289
|
||||
|
||||
#define IMX8MQ_CLK_END 290
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user