From 5e5da30f2e255f14c3098723fe171e6aec8d7db0 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 11 Apr 2025 11:44:25 +0530 Subject: [PATCH 01/86] arm64: dts: ti: k3-j784s4-evm-usxgmii-exp1-exp2: drop pinctrl-names The "pinctrl-names" property is not required since it doesn't have an associated pinctrl configuration. Hence, drop it. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250411061425.640718-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso index d5f8c8531923..424628c63c2d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -24,7 +24,6 @@ aliases { }; &main_cpsw0 { - pinctrl-names = "default"; status = "okay"; }; From 9d76be5828be44ed7a104cc21b4f875be4a63322 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 17 Apr 2025 18:02:43 +0530 Subject: [PATCH 02/86] arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1" In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree nodes in the SoC file, enable them in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250417123246.2733923-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 2127316f36a3..0bf2e1821662 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -843,6 +843,10 @@ &serdes_ln_ctrl { ; }; +&serdes_wiz0 { + status = "okay"; +}; + &serdes0 { status = "okay"; serdes0_usb_link: phy@0 { @@ -854,6 +858,10 @@ serdes0_usb_link: phy@0 { }; }; +&serdes_wiz1 { + status = "okay"; +}; + &serdes1 { status = "okay"; serdes1_pcie_link: phy@0 { From 320d8a84f6f045dc876d4c2983f9024c7ac9d6df Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 17 Apr 2025 18:02:44 +0530 Subject: [PATCH 03/86] arm64: dts: ti: k3-j722s-main: Disable "serdes_wiz0" and "serdes_wiz1" Since "serdes0" and "serdes1" which are the sub-nodes of "serdes_wiz0" and "serdes_wiz1" respectively, have been disabled in the SoC file already, and, given that these sub-nodes will only be enabled in a board file if the board utilizes any of the SERDES instances and the peripherals bound to them, we end up in a situation where the board file doesn't explicitly disable "serdes_wiz0" and "serdes_wiz1". As a consequence of this, the following errors show up when booting Linux: wiz bus@f0000:phy@f000000: probe with driver wiz failed with error -12 ... wiz bus@f0000:phy@f010000: probe with driver wiz failed with error -12 To not only fix the above, but also, in order to follow the convention of disabling device-tree nodes in the SoC file and enabling them in the board files for those boards which require them, disable "serdes_wiz0" and "serdes_wiz1" device-tree nodes. Fixes: 628e0a0118e6 ("arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250417123246.2733923-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 6850f50530f1..beda9e40e931 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -32,6 +32,8 @@ serdes_wiz0: phy@f000000 { assigned-clocks = <&k3_clks 279 1>; assigned-clock-parents = <&k3_clks 279 5>; + status = "disabled"; + serdes0: serdes@f000000 { compatible = "ti,j721e-serdes-10g"; reg = <0x0f000000 0x00010000>; @@ -70,6 +72,8 @@ serdes_wiz1: phy@f010000 { assigned-clocks = <&k3_clks 280 1>; assigned-clock-parents = <&k3_clks 280 5>; + status = "disabled"; + serdes1: serdes@f010000 { compatible = "ti,j721e-serdes-10g"; reg = <0x0f010000 0x00010000>; From 3f7523bf8c35f96e0309d420d9f89e300c97fc20 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 17 Apr 2025 18:02:45 +0530 Subject: [PATCH 04/86] arm64: dts: ti: k3-j722s-main: Don't disable serdes0 and serdes1 Since serdes0 and serdes1 are the child nodes of serdes_wiz0 and serdes_wiz1 respectively, and, given that serdes_wiz0 and serdes_wiz1 are already disabled, it is not necessary to disable serdes0 and serdes1. Moreover, having serdes_wiz0/serdes_wiz1 enabled and serdes0/serdes1 disabled is not a working configuration. Hence, remove 'status = "disabled"' from the serdes0 and serdes1 nodes. Suggested-by: Udit Kumar Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250417123246.2733923-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index beda9e40e931..562dfbdf449d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -52,8 +52,6 @@ serdes0: serdes@f000000 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ }; }; @@ -92,8 +90,6 @@ serdes1: serdes@f010000 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ }; }; From 2a36e8656836f5897508e61d46d22fe344af6426 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 17 Apr 2025 18:02:46 +0530 Subject: [PATCH 05/86] arm64: dts: ti: k3-j722s-evm: Drop redundant status within serdes0/serdes1 Since serdes0 and serdes1 are now enabled by default within the SoC file, it is no longer necessary to enable them in the board file. Hence, remove the redundant 'status = "okay"' within the serdes0 and serdes1 device-tree nodes. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250417123246.2733923-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 0bf2e1821662..34b9d190800e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -848,7 +848,6 @@ &serdes_wiz0 { }; &serdes0 { - status = "okay"; serdes0_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; @@ -863,7 +862,6 @@ &serdes_wiz1 { }; &serdes1 { - status = "okay"; serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; From 97b67cc102dc2cc8aa39a569c22a196e21af5a21 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:22 +0530 Subject: [PATCH 06/86] arm64: dts: ti: k3-j721e-sk: Add DT nodes for power regulators Add device tree nodes for two power regulators on the J721E SK board. vsys_5v0: A fixed regulator representing the 5V supply output from the LM61460 and vdd_sd_dv: A GPIO-controlled TLV71033 regulator. J721E-SK schematics: https://www.ti.com/lit/zip/sprr438 Fixes: 1bfda92a3a36 ("arm64: dts: ti: Add support for J721E SK") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250415111328.3847502-2-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 440ef57be294..ffef3d1cfd55 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -184,6 +184,17 @@ vsys_3v3: fixedregulator-vsys3v3 { regulator-boot-on; }; + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of LM61460 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + vdd_mmc1: fixedregulator-sd { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -211,6 +222,20 @@ vdd_sd_dv_alt: gpio-regulator-tps659411 { <3300000 0x1>; }; + vdd_sd_dv: gpio-regulator-TLV71033 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 118 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + transceiver1: can-phy1 { compatible = "ti,tcan1042"; #phy-cells = <0>; @@ -613,6 +638,12 @@ J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ + >; + }; + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ From 7edf0a4d3bb7f5cd84f172b76c380c4259bb4ef8 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:23 +0530 Subject: [PATCH 07/86] arm64: dts: ti: k3-am68-sk: Fix regulator hierarchy Update the vin-supply of the TLV71033 regulator from LM5141 (vsys_3v3) to LM61460 (vsys_5v0) to match the schematics. Add a fixed regulator node for the LM61460 5V supply to support this change. AM68-SK schematics: https://www.ti.com/lit/zip/sprr463 Fixes: a266c180b398 ("arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Neha Malcom Francis Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250415111328.3847502-3-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 11522b36e0ce..5fa70a874d7b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -44,6 +44,17 @@ vusb_main: regulator-vusb-main5v0 { regulator-boot-on; }; + vsys_5v0: regulator-vsys5v0 { + /* Output of LM61460 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + vsys_3v3: regulator-vsys3v3 { /* Output of LM5141 */ compatible = "regulator-fixed"; @@ -76,7 +87,7 @@ vdd_sd_dv: regulator-tlv71033 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - vin-supply = <&vsys_3v3>; + vin-supply = <&vsys_5v0>; gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; From 24ab76e55ef15450c6681a2b5db4d78f45200939 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:24 +0530 Subject: [PATCH 08/86] arm64: dts: ti: k3-j721e-sk: Remove clock-names property from IMX219 overlay The IMX219 sensor device tree bindings do not include a clock-names property. Remove the incorrectly added clock-names entry to avoid dtbs_check warnings. Fixes: f767eb918096 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Neha Malcom Francis Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20250415111328.3847502-4-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso index 47bb5480b5b0..4a395d1209c8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -34,7 +34,6 @@ imx219_0: imx219-0@10 { reg = <0x10>; clocks = <&clk_imx219_fixed>; - clock-names = "xclk"; port { csi2_cam0: endpoint { @@ -56,7 +55,6 @@ imx219_1: imx219-1@10 { reg = <0x10>; clocks = <&clk_imx219_fixed>; - clock-names = "xclk"; port { csi2_cam1: endpoint { From c6a20a250200da6fcaf80fe945b7b92cba8cfe0f Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:25 +0530 Subject: [PATCH 09/86] arm64: dts: ti: k3-j721e-sk: Add requiried voltage supplies for IMX219 The device tree overlay for the IMX219 sensor requires three voltage supplies to be defined: VANA (analog), VDIG (digital core), and VDDL (digital I/O). Add the corresponding voltage supply definitions to avoid dtbs_check warnings. Fixes: f767eb918096 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Link: https://lore.kernel.org/r/20250415111328.3847502-5-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso index 4a395d1209c8..4eb3cffab032 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -19,6 +19,33 @@ clk_imx219_fixed: imx219-xclk { #clock-cells = <0>; clock-frequency = <24000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vdd_sd_dv>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_sd_dv>; + regulator-always-on; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_sd_dv>; + regulator-always-on; + }; }; &csi_mux { @@ -34,6 +61,9 @@ imx219_0: imx219-0@10 { reg = <0x10>; clocks = <&clk_imx219_fixed>; + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; port { csi2_cam0: endpoint { @@ -55,6 +85,9 @@ imx219_1: imx219-1@10 { reg = <0x10>; clocks = <&clk_imx219_fixed>; + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; port { csi2_cam1: endpoint { From c68ab54a89a8c935732589a35ea2596e2329f167 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:26 +0530 Subject: [PATCH 10/86] arm64: dts: ti: k3-am62x: Remove clock-names property from IMX219 overlay The IMX219 sensor device tree bindings do not include a clock-names property. Remove the incorrectly added clock-names entry to avoid dtbs_check warnings. Fixes: 4111db03dc05 ("arm64: dts: ti: k3-am62x: Add overlay for IMX219") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Neha Malcom Francis Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20250415111328.3847502-6-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso index 76ca02127f95..7a0d35eb04d3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso @@ -39,7 +39,6 @@ ov5640: camera@10 { reg = <0x10>; clocks = <&clk_imx219_fixed>; - clock-names = "xclk"; reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>; From 7b75dd2029ee01a8c11fcf4d97f3ccebbef9f8eb Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:27 +0530 Subject: [PATCH 11/86] arm64: dts: ti: k3-am62x: Rename I2C switch to I2C mux in IMX219 overlay The IMX219 device tree overlay incorrectly defined an I2C switch instead of an I2C mux. According to the DT bindings, the correct terminology and node definition should use "i2c-mux" instead of "i2c-switch". Hence, update the same to avoid dtbs_check warnings. Fixes: 4111db03dc05 ("arm64: dts: ti: k3-am62x: Add overlay for IMX219") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Neha Malcom Francis Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20250415111328.3847502-7-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso index 7a0d35eb04d3..dd090813a32d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso @@ -22,7 +22,7 @@ &main_i2c2 { #size-cells = <0>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9543"; #address-cells = <1>; #size-cells = <0>; From b22cc402d38774ccc552d18e762c25dde02f7be0 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Tue, 15 Apr 2025 16:43:28 +0530 Subject: [PATCH 12/86] arm64: dts: ti: k3-am62x: Rename I2C switch to I2C mux in OV5640 overlay The OV5640 device tree overlay incorrectly defined an I2C switch instead of an I2C mux. According to the DT bindings, the correct terminology and node definition should use "i2c-mux" instead of "i2c-switch". Hence, update the same to avoid dtbs_check warnings. Fixes: 635ed9715194 ("arm64: dts: ti: k3-am62x: Add overlays for OV5640") Cc: stable@vger.kernel.org Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Neha Malcom Francis Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20250415111328.3847502-8-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso | 2 +- arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso index ccc7f5e43184..7fc7c95f5cd5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -22,7 +22,7 @@ &main_i2c2 { #size-cells = <0>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9543"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso index 4eaf9d757dd0..b6bfdfbbdd98 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -22,7 +22,7 @@ &main_i2c2 { #size-cells = <0>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9543"; #address-cells = <1>; #size-cells = <0>; From c574db0b68a600f9548f0ef7bcba723562713587 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:01:57 +0530 Subject: [PATCH 13/86] dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property Add a pattern property for pcie-ctrl which can be part of this controller. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Change description and add example] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250402113201.151195-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../bindings/soc/ti/ti,j721e-system-controller.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2..13b6b6fa5dee 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -68,6 +68,11 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + The node corresponding to PCIe control register. + required: - compatible - reg @@ -110,5 +115,10 @@ examples: compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; }; ... From df2210b2da139e3a733bd7bd1406cd74d39d59a7 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:01:58 +0530 Subject: [PATCH 14/86] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe nodes. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +- .../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++--- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso index 4062709d6579..a8a502a6207f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso @@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 { reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso index a8cccdcf3e3b..436085157a69 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso @@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index af3d730154ac..d7263ad43163 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x50>; @@ -946,7 +966,7 @@ pcie0_rc: pcie@2900000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -975,7 +995,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -1004,7 +1024,7 @@ pcie2_rc: pcie@2920000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -1033,7 +1053,7 @@ pcie3_rc: pcie@2930000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; From 1f326fb84a6074772f01dc63ed4d3eb791682479 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:01:59 +0530 Subject: [PATCH 15/86] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-4-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso index 3cc315a0e084..281076d905f3 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso @@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ab510a0605f..dbb000657377 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x20>; @@ -764,7 +769,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; From 755e47a71f9dbfbdb33fc18d20a74b7804a20acf Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:02:00 +0530 Subject: [PATCH 16/86] arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-am68-sk-base-board-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-5-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso index 455736e378cc..ba521d661144 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso @@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso index 5ff390915b75..8c2cd99cf2b4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -38,7 +38,7 @@ pcie1_ep: pcie-ep@2910000 { reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 92bf48fdbeba..c0c2b95d4652 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -57,6 +57,11 @@ phy_gmii_sel_cpsw: phy@34 { #phy-cells = <1>; }; + pcie1_ctrl: pcie-ctrl@74 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x74 0x4>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible = "reg-mux"; reg = <0x80 0x10>; @@ -1399,7 +1404,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; From 4e7ad3b4464571d7bec6869944151b27cce44435 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 2 Apr 2025 17:02:01 +0530 Subject: [PATCH 17/86] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250402113201.151195-6-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++- arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 324eb44c258d..d872a624601c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -51,6 +51,11 @@ chipid@14 { reg = <0x00000014 0x4>; }; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x4>; @@ -1036,7 +1041,7 @@ pcie0_rc: pcie@f102000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <2>; num-lanes = <1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso index 6b029539e0db..432751774853 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso @@ -46,6 +46,6 @@ pcie0_ep: pcie-ep@f102000 { max-functions = /bits/ 8 <1>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; }; }; From bdd158389dac25ff36e041ff28591aca769f403c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 1 Apr 2025 10:32:46 +0200 Subject: [PATCH 18/86] arm64: dts: ti: k3-am62p-j722s: Add rng node Add the node for the random number generator inside the crypto module. Marked reserved since the default usage is with the RNG node being controlled by OP-TEE. Signed-off-by: Michael Walle Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250401083246.3228964-1-mwalle@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 6e3beb5c2e01..7b65538110e8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -227,9 +227,18 @@ crypto: crypto@40900000 { reg = <0x00 0x40900000 0x00 0x1200>; #address-cells = <2>; #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x0 0x7d>; + interrupts = ; + status = "reserved"; + }; }; secure_proxy_sa3: mailbox@43600000 { From c026c5e6ed9323304b88bbb2feb6f039eca114d0 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 8 Apr 2025 22:26:55 +0200 Subject: [PATCH 19/86] arm64: dts: ti: k3-am625-verdin: Add EEPROM compatible fallback According to the AT24 EEPROM bindings the compatible string should contain first the actual manufacturer, and second the corresponding atmel model. Add the atmel compatible fallback accordingly. Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250408202655.6329-1-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index fcc4cb2e9389..2b5f5e50b578 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -114,7 +114,7 @@ sensor@4f { /* EEPROM */ eeprom@57 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi index 7372d392ec8a..9a2483cf5d70 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -118,7 +118,7 @@ sensor@4f { /* EEPROM */ eeprom@57 { - compatible = "st,24c02"; + compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; }; From 3a5ff313ac521ff034f07ea6687ffb3f2229d62a Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 15 Apr 2025 17:59:39 -0500 Subject: [PATCH 20/86] dt-bindings: arm: ti: Add PocketBeagle2 This board is based on ti,am625 family using the am6232 and am6254 variations. https://www.beagleboard.org/boards/pocketbeagle-2 https://openbeagle.org/pocketbeagle/pocketbeagle-2 Signed-off-by: Robert Nelson Reviewed-by: Dhruva Gole Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250415225940.3899486-1-robertcnelson@gmail.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c8..b7f6cd8d4b9e 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -46,6 +46,7 @@ properties: - description: K3 AM625 SoC items: - enum: + - beagle,am62-pocketbeagle2 - beagle,am625-beagleplay - ti,am625-sk - ti,am62-lp-sk From 92d8c028aa924286f10ac75b7f9e8edfc9ed432b Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 15 Apr 2025 17:59:40 -0500 Subject: [PATCH 21/86] arm64: dts: ti: Add k3-am62-pocketbeagle2 BeagleBoard.org PocketBeagle 2 is an upgraded version of the popular PocketBeagle. It is based on Texas Instruments AM6232 or AM6254 SoC. Its dual or quad A53 cores can provide higher performance than classic PocketBeagle. The new design comes with pre-soldered headers, a 3-pin JST-SH 1.00mm UART debug port, a USB-C port, Texas Instruments MSPM0L1105 Cortex-M0+ MCU for ADC, 512MB RAM, and a LiPo Battery charger. MSPM0L1105 firmware source: https://openbeagle.org/pocketbeagle/mspm0-adc-eeprom * EEPROM 24c32 emulation * ADC ad7291 emulation https://www.beagleboard.org/boards/pocketbeagle-2 https://openbeagle.org/pocketbeagle/pocketbeagle-2 Signed-off-by: Robert Nelson Tested-by: Dhruva Gole Reviewed-by: Bryan Brattlof Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20250415225940.3899486-2-robertcnelson@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 521 ++++++++++++++++++ 2 files changed, 522 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 03d4cecfc001..4f8fcb69a2c1 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts new file mode 100644 index 000000000000..2e4cf65ee323 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * https://www.beagleboard.org/boards/pocketbeagle-2 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2025 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "beagle,am62-pocketbeagle2", "ti,am625"; + model = "BeagleBoard.org PocketBeagle2"; + + aliases { + serial0 = &wkup_uart0; + serial1 = &main_uart1; + serial2 = &main_uart6; + serial3 = &main_uart0; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + i2c0 = &main_i2c0; + i2c2 = &main_i2c2; + i2c3 = &wkup_i2c0; + }; + + chosen { + stdout-path = &main_uart6; + }; + + memory@80000000 { + /* 512MB RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x20000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vsys_5v0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_5v0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-4 { + compatible = "regulator-gpio"; + regulator-name = "sd_hs200_switch"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vdd_3v3>; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + adc_vref: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + bootph-all; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + default-state = "on"; + bootph-all; + }; + + led-2 { + function = LED_FUNCTION_DISK_ACTIVITY; + color = ; + linux,default-trigger = "mmc1"; + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + bootph-all; + }; + + led-3 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + bootph-all; + }; + + led-4 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + bootph-all; + }; + }; +}; + +&main_pmx0 { + led_pins_default: led-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x000c, PIN_OUTPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ + AM62X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ + AM62X_IOPAD(0x0014, PIN_OUTPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ + AM62X_IOPAD(0x0018, PIN_OUTPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ + >; + bootph-all; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + bootph-all; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ + >; + bootph-all; + }; + + main_uart6_pins_default: main-uart6-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 7) /* (D17/C15) MMC1_SDCD.GPIO1_48 */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO1_49 */ + >; + bootph-all; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ + >; + bootph-all; + }; + + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ + >; + bootph-all; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + bootph-all; + }; + + epwm2_pins_default: epwm2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_OUTPUT, 8) /* (B17) I2C1_SCL.EHRPWM2_A */ + >; + }; +}; + +&epwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&epwm2_pins_default>; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + bootph-pre-ram; + status = "reserved"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart6_pins_default>; + bootph-all; + status = "okay"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + bootph-all; + status = "okay"; + + ad7291: adc@20 { + /* Emulated with MSPM0L1105 */ + compatible = "adi,ad7291"; + reg = <0x20>; + vref-supply = <&adc_vref>; + }; + + eeprom: eeprom@50 { + /* Emulated with MSPM0L1105 */ + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + bootph-all; + status = "okay"; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ + >; + bootph-all; + }; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + disable-wp; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + bootph-all; + ti,fails-without-test-cd; + status = "okay"; +}; + +&usbss0 { + bootph-all; + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + /* This is a Type-C socket, but wired as USB 2.0 */ + dr_mode = "peripheral"; + bootph-all; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + /* + * Default set here is compatible with original PocketBeagle, + * Expansion boards assumed this was pre-setup as host. + */ + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; + status = "reserved"; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <100000>; + bootph-all; + status = "okay"; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vsys_5v0>; + buck2-supply = <&vsys_5v0>; + buck3-supply = <&vsys_5v0>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vdd_3v3>; + ldo4-supply = <&vdd_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + bootph-all; + system-power-controller; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* + * Regulator is left as is unused, vdd_sd + * is controlled via GPIO with bypass config + * as per the NVM configuration + */ + regulator-name = "VDD_SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDA_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; From 6a7023118fd7901d8b7967388923604d5d646cca Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 11 Apr 2025 15:39:50 -0500 Subject: [PATCH 22/86] arm64: dts: ti: k3-am67a-beagley-ai: Add bootph for main_gpio1 main_gpio1 controls the voltage for the SDcard from 3.3v to 1.8v. This is required for proper operation of SDcard through various boot stages. Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250411203950.2859356-1-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index 9be6bba28c26..bf9b23df1da2 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -309,6 +309,7 @@ &cpsw_port1 { }; &main_gpio1 { + bootph-all; status = "okay"; }; From bcbc3d40dc62dd616e409b8b18c13d5b55fca6af Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 9 Apr 2025 15:38:53 +0530 Subject: [PATCH 23/86] arm64: dts: ti: k3-j784s4-j742s2-evm: Add overlay to enable USB0 Type-A The USB0 instance of the USB controller on both the J742S2 EVM and the J784S4 EVM supports a single USB interface at a time among the following: 1. USB3.1 Gen1 Type C interface 2. Two USB2.0 Type A interfaces via an on-board USB Hub. By default, the USB3.1 Gen1 Type C interface is supported on both of the EVMs. Enable the USB2.0 Type A interface by configuring the USB2.0_MUX_SEL mux. Additionally, set the Dual-Role Mode to Host since a Type-A interface is only associated with the Host Mode of operation. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250409100853.4179934-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 7 +++++ .../ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso | 29 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4f8fcb69a2c1..73cec51d88aa 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-j742s2-evm-usb0-type-a.dtbo # Boards with J742S2 SoC dtb-$(CONFIG_ARCH_K3) += k3-j742s2-evm.dtb @@ -213,10 +214,14 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usb0-type-a-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -247,8 +252,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usb0-type-a.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtb # Enable support for device-tree overlays diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso new file mode 100644 index 000000000000..ba15d72d86d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-usb0-type-a.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB on J784S4 and J742S2 EVMs for + * Host Mode of operation with the Type-A Connector. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * J742S2 EVM Product Link: https://www.ti.com/tool/J742S2XH01EVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&exp2 { + p12-hog { + /* P12 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode = "host"; +}; From 8a0bba5b6730a1491a111bf54de5d8dcc23c8e10 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 24 Apr 2025 13:33:28 +0530 Subject: [PATCH 24/86] arm64: dts: ti: k3-j721e-common-proc-board-infotainment: Update to comply with device tree schema Fix hdmi-connector and tfp bridge node as per the bindings, - Remove 'digital' property which is required for DVI connector not HDMI - Add 'ti,deskew' property which is a required property - Fix ports property for tfp410 bridge - Change node names appropriately Redefine the ports for dss and for k3-j721e-common-proc-board.dts, add reg property for the port (@0) to get rid of dtbs_check warnings in infotainment overlay when ports for dss are re-defined. Signed-off-by: Jayesh Choudhary Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250424080328.57671-1-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- ...-j721e-common-proc-board-infotainment.dtso | 57 +++++++++++-------- .../dts/ti/k3-j721e-common-proc-board.dts | 6 +- 2 files changed, 38 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso index 65a7e54f0884..e4e5f941f20b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board-infotainment.dtso @@ -15,12 +15,11 @@ #include "k3-pinctrl.h" &{/} { - hdmi-connector { + connector-hdmi { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; ddc-i2c-bus = <&main_i2c1>; - digital; /* P12 - HDMI_HPD */ hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>; @@ -31,28 +30,32 @@ hdmi_connector_in: endpoint { }; }; - dvi-bridge { - #address-cells = <1>; - #size-cells = <0>; + bridge-dvi { compatible = "ti,tfp410"; /* P10 - HDMI_PDn */ powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - tfp410_in: endpoint { - remote-endpoint = <&dpi_out0>; - pclk-sample = <1>; + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - tfp410_out: endpoint { - remote-endpoint = - <&hdmi_connector_in>; + tfp410_out: endpoint { + remote-endpoint = + <&hdmi_connector_in>; + }; }; }; }; @@ -148,17 +151,23 @@ p11-hog { &dss { pinctrl-names = "default"; pinctrl-0 = <&dss_vout0_pins_default>; -}; -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@1 { - reg = <1>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; - dpi_out0: endpoint { - remote-endpoint = <&tfp410_in>; + port@1 { + reg = <1>; + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 4421852161dd..e3d0ef6913b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -804,7 +804,11 @@ &dss { }; &dss_ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; From 5959618631fec502ec0963f4082d565f7fbfff04 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 21 Apr 2025 16:46:18 -0500 Subject: [PATCH 25/86] dt-bindings: mfd: ti,j721e-system-controller: Add compatible string for AM654 Add the child nodes that can be found under this node. Then as done for other similar devices (J7200 and J721s2) add support for the AM654 system controller to this binding. Signed-off-by: Andrew Davis Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250421214620.3770172-2-afd@ti.com Signed-off-by: Nishanth Menon --- .../bindings/soc/ti/ti,j721e-system-controller.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 13b6b6fa5dee..f3bd0be3b279 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - ti,am654-system-controller - ti,j7200-system-controller - ti,j721e-system-controller - ti,j721s2-system-controller @@ -73,6 +74,18 @@ patternProperties: description: The node corresponding to PCIe control register. + "^clock@[0-9a-f]+$": + type: object + $ref: /schemas/soc/ti/ti,am654-serdes-ctrl.yaml# + description: + This is the Serdes Control region. + + "^dss-oldi-io-ctrl@[0-9a-f]+$": + type: object + $ref: /schemas/mfd/syscon.yaml# + description: + This is the DSS OLDI CTRL region. + required: - compatible - reg From 4765253055cc8ab3fdc5f9eb5b121d867e209fb1 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 21 Apr 2025 16:46:19 -0500 Subject: [PATCH 26/86] arm64: dts: ti: k3-am65-main: Add system controller compatible Now that the TI K3 AM654 system controller bindings also cover the usage in the main domain, add its compatible to address dtbs_check complains: k3-am654-base-board.dtb: scm-conf@100000: compatible: ['syscon', 'simple-mfd'] is too short Signed-off-by: Jan Kiszka Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20250421214620.3770172-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 94a812a1355b..6d3c467d7038 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -479,7 +479,7 @@ sdhci1: mmc@4fa0000 { }; scm_conf: scm-conf@100000 { - compatible = "syscon", "simple-mfd"; + compatible = "ti,am654-system-controller", "syscon", "simple-mfd"; reg = <0 0x00100000 0 0x1c000>; #address-cells = <1>; #size-cells = <1>; From ae3ac9ffd59acf46b8934f4e7a5fa7a6803ac959 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 21 Apr 2025 16:46:20 -0500 Subject: [PATCH 27/86] arm64: dts: ti: am65x: Add missing power-supply for Rocktech-rk101 panel Add the 5v0 supply that is provided over the display panel cable and used by the LCD. This is required by "simple panels" or we get the following warning from DTBS_CHECK: k3-am654-gp-evm.dtb: display0: 'power-supply' is a required property Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20250421214620.3770172-4-afd@ti.com Signed-off-by: Nishanth Menon --- .../ti/k3-am654-base-board-rocktech-rk101-panel.dtso | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso index 364c57b3b3a0..7a3953d64fd8 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -15,8 +15,20 @@ #include &{/} { + vcc_5v0: lcd-regulator { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&evm_12v0>; + }; + display0 { compatible = "rocktech,rk101ii01d-ct"; + power-supply = <&vcc_5v0>; backlight = <&lcd_bl>; enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; port { From 3b62bd1fde50d54cc59015e14869e6cc3d6899e0 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 23 Apr 2025 20:46:12 +0530 Subject: [PATCH 28/86] arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix length of serdes_ln_ctrl Commit under Fixes corrected the "mux-reg-masks" property but did not update the "length" field of the "reg" property to account for the newly added register offsets which extend the region. Fix this. Fixes: 38e7f9092efb ("arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250423151612.48848-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 1944616ab357..1fc0a11c5ab4 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -77,7 +77,7 @@ pcie1_ctrl: pcie1-ctrl@4074 { serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; - reg = <0x00004080 0x30>; + reg = <0x00004080 0x50>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ From 5d15c4395fd360ab894a28c6a7c8ca44593cdc61 Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Wed, 23 Apr 2025 15:36:33 +0200 Subject: [PATCH 29/86] dt-bindings: arm: ti: Add bindings for PHYTEC AM68x based hardware Add devicetree bindings for the AM68x based phyCORE-AM68x/TDA4x SoM and the phyBOARD-Izar carrier board. Signed-off-by: Dominik Haller Reviewed-by: Wadim Egorov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250423133635.29897-1-d.haller@phytec.de Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index b7f6cd8d4b9e..a6d9fd0bcaba 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -140,6 +140,13 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J721s2 SoC Phytec SoM based boards + items: + - enum: + - phytec,am68-phyboard-izar + - const: phytec,am68-phycore-som + - const: ti,j721s2 + - description: K3 J722S SoC and Boards items: - enum: From 8bc3b1c8645213ffc22f48238e2f325cc4fa29d0 Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Wed, 23 Apr 2025 15:36:34 +0200 Subject: [PATCH 30/86] arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68x The phyCORE-AM68x/TDA4x [1] is a SoM (System on Module) featuring TI's AM68x/TDA4x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM68x/TDA4x (J721S2) family. A reference carrier board design, called phyBOARD-Izar is used for the phyCORE-AM68x/TDA4x development kit [2]. Supported features: * Debug UART * 2x SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * 2x I2C GPIO Expander * LEDs * USB 5 Gbit/s * PCIe For more details see the product pages for the SoM and the development kit: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ [2] https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ Signed-off-by: Dominik Haller Reviewed-by: Wadim Egorov Reviewed-by: Udit Kumar Acked-by: Moteen Shah Link: https://lore.kernel.org/r/20250423133635.29897-2-d.haller@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am68-phyboard-izar.dts | 575 +++++++++++++++++ .../boot/dts/ti/k3-am68-phycore-som.dtsi | 601 ++++++++++++++++++ 3 files changed, 1177 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 73cec51d88aa..a48e7608de8b 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC +dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts new file mode 100644 index 000000000000..41c8f8526e15 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + * + * https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "k3-am68-phycore-som.dtsi" + +#include "k3-serdes.h" + +/ { + compatible = "phytec,am68-phyboard-izar", + "phytec,am68-phycore-som", "ti,j721s2"; + model = "PHYTEC phyBOARD-Izar-AM68x"; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart8; + serial3 = &main_uart2; + mmc1 = &main_sdhci1; + ethernet0 = &cpsw_port1; + }; + + chosen { + stdout-path = &main_uart8; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + vcc_12v0: regulator-12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "VCC_IN"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_1v8: regulator-vcc-1v8 { + /* Output of TLV7158P */ + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-vcc-3v3 { + /* Output of SiC431 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + }; + + vcc_5v0: regulator-vcc-5v0 { + /* Output of LM5116 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_12v0>; + }; +}; + +&main_pmx0 { + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (V27) MCASP1_AXR1.I2C2_SCL */ + J721S2_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (W27) MCASP1_AXR2.I2C2_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ + >; + }; + + main_mcan1_pins_default: main-mcan1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c8, PIN_INPUT, 4) /* (AD28) EXT_REFCLK1.MCAN1_RX */ + J721S2_IOPAD(0x06c, PIN_OUTPUT, 0) /* (V26) MCAN1_TX */ + >; + }; + + main_mcan13_pins_default: main-mcan13-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_INPUT, 9) /* (AG25) TIMER_IO1.MCAN13_RX */ + J721S2_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AE28) MCAN13_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + bootph-all; + }; + + main_spi6_pins_default: main-spi6-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x030, PIN_INPUT, 8) /* (T26) GPIO0_12.SPI6_CLK */ + J721S2_IOPAD(0x080, PIN_INPUT, 8) /* (U26) MCASP0_AXR4.SPI6_CS2 */ + J721S2_IOPAD(0x0c4, PIN_OUTPUT, 8) /* (AB26) ECAP0_IN_APWM_OUT.SPI6_D0 */ + J721S2_IOPAD(0x074, PIN_INPUT, 8) /* (R28) MCAN2_TX.SPI6_D1 */ + J721S2_IOPAD(0x0dc, PIN_OUTPUT, 7) /* (AH26) SPI0_D1.GPIO0_55 */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x05c, PIN_INPUT, 11) /* (AA26) MCASP2_AXR0.UART1_CTSn */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 11) /* (AC27) MCASP2_AXR1.UART1_RTSn */ + J721S2_IOPAD(0x054, PIN_INPUT, 11) /* (Y27) MCASP2_ACLKX.UART1_RXD */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 11) /* (AA27) MCASP2_AFSX.UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d8, PIN_INPUT, 11) /* (AG26) SPI0_D0.UART2_RXD */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 11) /* (U28) MCAN0_RX.UART2_TXD */ + >; + }; + + main_uart8_pins_default: main-uart8-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + bootph-all; + }; +}; + +&wkup_pmx1 { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x038, PIN_INPUT, 0) /* (B27) MCU_SPI0_CLK */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B26) MCU_SPI0_CS0 */ + J721S2_WKUP_IOPAD(0x068, PIN_INPUT, 2) /* (C23) WKUP_GPIO0_4.MCU_SPI0_CS3 */ + J721S2_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (D24) MCU_SPI0_D0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 0) /* (B25) MCU_SPI0_D1 */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + bootph-all; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + }; +}; + +&i2c_som_rtc { + trickle-resistor-ohms = <3000>; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + status = "okay"; + + exp1: gpio@20 { + compatible = "nxp,pca9672"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HALF/nFULL_EN", "RS485/nRS232_EN", "MCU_ETH_nRESET", "", + "PCIe_nRESET", "USB2.0-Hub_nRESET", "USB3.0-Hub_nRESET", "PEB_AV_BL_EN"; + interrupt-parent = <&main_gpio0>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "RPI_GPIO4", "RPI_GPIO5", "RPI_GPIO6", "RPI_GPIO19", + "RPI_GPIO20", "RPI_GPIO21", "RPI_GPIO22", "RPI_GPIO23", + "RPI_GPIO24", "RPI_GPIO25", "RPI_GPIO26", "RPI_GPIO20", + "LVDS_BL_nEN", "LVDS_REG_nEN", "CSI_CAM0_nRESET", "CSI_CAM1_nRESET", + "CSI0_CTRL1", "CSI0_CTRL2", "CSI0_CTRL3", "CSI0_CTRL4", + "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3", "CSI1_CTRL4"; + interrupt-parent = <&main_gpio0>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; + }; +}; + +/* CSI0 + RPI */ +&main_i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; +}; + +/* CSI1 + PCIe */ +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_mcan13 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan13_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&main_mcan16 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan16_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; + +/* SD-Card */ +&main_sdhci1 { + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&main_spi6 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi6_pins_default>; + cs-gpios = <&main_gpio0 55 GPIO_ACTIVE_LOW>; + ti,spi-num-cs = <1>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + uart-has-rtscts; + status = "okay"; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; + status = "okay"; +}; + +&main_uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; + status = "okay"; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&mcu_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + status = "okay"; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver4>; + status = "okay"; +}; + +/* RPI-Header */ +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +/* RPI-Header */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + uart-has-rtscts; + status = "okay"; +}; + +&ospi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,phy-type = ; + }; + + serdes0_usb_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + resets = <&serdes_wiz0 2>; + cdns,phy-type = ; + }; +}; + +&tscadc0 { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + status = "okay"; + + adc { + ti,adc-channels = <3 4 5 6 7>; + }; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&wkup_i2c0 { + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-1 { + label = "user-led1"; + type = ; + }; + + led-2 { + label = "user-led2"; + type = ; + }; + + led-3 { + label = "user-led3"; + type = ; + }; + }; +}; + +/* Shared with TIFS */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi new file mode 100644 index 000000000000..fd715fee8170 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + * + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ + */ + +/dts-v1/; + +#include +#include +#include "k3-j721s2.dtsi" + +/ { + compatible = "phytec,am68-phycore-som", "ti,j721s2"; + model = "PHYTEC phyCORE-AM68x"; + + aliases { + ethernet1 = &main_cpsw_port1; + mmc0 = &main_sdhci0; + rtc0 = &i2c_som_rtc; + }; + + memory@80000000 { + device_type = "memory"; + /* 4GB RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + vdd_sd_dv: regulator-sd { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "VDD_SD_DV"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 1 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0>, + <1800000 0x1>; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_pins_default: main-cpsw-mdio-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x004, PIN_OUTPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + >; + bootph-all; + }; +}; + +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + >; + }; +}; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ + >; + bootph-all; + }; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; + status = "okay"; +}; + +&c71_1 { + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; + status = "okay"; +}; + +&mailbox0_cluster0 { + interrupts = <436>; + status = "okay"; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + status = "okay"; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&main_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; + status = "okay"; +}; + +&main_cpsw_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_pins_default>; + status = "okay"; + + phy1: ethernet-phy@0 { + reg = <0>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + }; +}; + +&main_cpsw_port1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + + temperature-sensor@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +/* eMMC */ +&main_sdhci0 { + non-removable; + ti,driver-strength-ohm = <50>; + bootph-all; + status = "okay"; +}; + +/* SD card */ +&main_sdhci1 { + vqmmc-supply = <&vdd_sd_dv>; + bootph-all; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + bootph-all; + }; +}; + +&wkup_gpio0 { + status = "okay"; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu_avs: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + bootph-pre-ram; + }; + + pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + buck12-supply = <&vcc_3v3>; + buck3-supply = <&vcc_3v3>; + buck4-supply = <&vcc_3v3>; + buck5-supply = <&vcc_3v3>; + ldo1-supply = <&vcc_3v3>; + ldo2-supply = <&vcc_3v3>; + ldo3-supply = <&vcc_3v3>; + ldo4-supply = <&vcc_3v3>; + ti,primary-pmic; + + regulators { + bucka12: buck12 { + regulator-name = "VDD_DDR_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka3: buck3 { + regulator-name = "VDD_RAM_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka4: buck4 { + regulator-name = "VDD_IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + bucka5: buck5 { + regulator-name = "VDD_MCU_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa1: ldo1 { + regulator-name = "VDD_MCUIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa2: ldo2 { + regulator-name = "VDD_MCUIO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa3: ldo3 { + regulator-name = "VDDA_DLL_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldoa4: ldo4 { + regulator-name = "VDDA_MCU_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + bootph-all; + }; + + som_eeprom_opt: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; From b2fd55f906ff70a39e67d5ad770774622164bef1 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 21 Apr 2025 19:08:49 -0500 Subject: [PATCH 31/86] arm64: dts: ti: k3-am62p5-sk: Enable PWM PWM signals can be routed to the user expansion header on am62p5 SK. Enable eCAP0, eCAP1, eHRPWM0, eHRPWM1 and route the output PWM signals to pins on J4 header. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250422000851.4118545-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index d29f524600af..c2f55cc5a8eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -356,6 +356,32 @@ wlan_en_pins_default: wlan-en-default-pins { AM62PX_IOPAD(0x0124, PIN_INPUT, 7) /* (J25) MMC2_SDCD.GPIO0_71 */ >; }; + + main_ecap1_pins_default: main-ecap1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (E24) MCASP0_AXR1.ECAP1_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (F24) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + + main_epwm0_pins_default: main-epwm0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (D20) SPI0_CS0.EHRPWM0_A */ + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ + >; + }; + + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (B21) SPI0_CLK.EHRPWM1_A */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 2) /* (B20) SPI0_D0.EHRPWM1_B */ + >; + }; }; &main_i2c0 { @@ -683,3 +709,31 @@ &mcu_gpio0 { &mcu_gpio_intr { status = "reserved"; }; + +&ecap1 { + /* P36 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* P11 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; + +&epwm0 { + /* P24/P26 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm0_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* P23/P19 of J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; From 5aec1169b53969d07cc288814f7eebd2ef01f9a0 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 21 Apr 2025 19:08:50 -0500 Subject: [PATCH 32/86] arm64: dts: ti: k3-am62a7-sk: Enable PWM PWM signals can be routed to the user expansion header on am62a7 SK. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250422000851.4118545-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 1c9d95696c83..a9557ee73b83 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -383,6 +383,25 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; + + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01b8, PIN_OUTPUT, 3) /* (C16) SPI0_CS1.ECAP0_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (A19) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62AX_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (B20) MCASP0_AXR0.EHRPWM1_B */ + >; + }; }; &mcu_pmx0 { @@ -741,3 +760,24 @@ dpi1_out: endpoint { }; }; }; + +&ecap0 { + /* P26 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* P11 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* P36/P33 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; From d864bb528a6725e775d564fd4430762acbb9dd0d Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 21 Apr 2025 19:08:51 -0500 Subject: [PATCH 33/86] arm64: dts: ti: k3-am625-sk: Enable PWM PWM signals can be routed to the user expansion header on am625 SK and am62 lp sk. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250422000851.4118545-4-jm@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index d52cb2a5a589..20d1437f253d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -303,6 +303,25 @@ AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ >; }; + + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 3) /* (C13) SPI0_CS1.ECAP0_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (B20) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (E18) MCASP0_AXR0.EHRPWM1_B */ + >; + }; }; &mcu_pmx0 { @@ -560,3 +579,24 @@ &mcu_gpio0 { &mcu_gpio_intr { status = "reserved"; }; + +&ecap0 { + /* P26 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* P11 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* P36/P33 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; From db3cd905b8c8cd40f15a34e30a225704bb8a2fcb Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 10:14:52 -0500 Subject: [PATCH 34/86] arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC boot The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. For eMMC and SD boot modes, voltage regulator nodes, io-expander nodes, gpio nodes, and MMC nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot and eMMC boot. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah Link: https://lore.kernel.org/r/20250429151454.4160506-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 8e9fc00a6b3c..aafdb90c0eb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -69,6 +69,7 @@ vddshv_sdio: regulator-4 { gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; + bootph-all; }; }; @@ -77,12 +78,14 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; + bootph-all; }; main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -118,6 +121,7 @@ exp1: gpio@22 { pinctrl-names = "default"; pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; }; exp2: gpio@23 { @@ -229,6 +233,14 @@ &tlv320aic3106 { DVDD-supply = <&buck2_reg>; }; +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + &gpmc0 { ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index a9557ee73b83..22be41d46eb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -313,6 +313,7 @@ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; main_mmc1_pins_default: main-mmc1-default-pins { @@ -634,6 +635,7 @@ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; + bootph-all; }; &sdhci1 { From d16e7d34352c4107a81888e9aab4ea4748076e70 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 10:14:53 -0500 Subject: [PATCH 35/86] arm64: dts: ti: k3-am62*: Add non-removable flag for eMMC EMMC device is non-removable so add 'non-removable' DT property to avoid having to redetect the eMMC after suspend/resume. Signed-off-by: Judith Mendez Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250429151454.4160506-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index a5469f2712f0..1c8b4d13fb49 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -832,6 +832,7 @@ &main_spi2 { &sdhci0 { bootph-all; + non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index c2f55cc5a8eb..ab06cc42b4f2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -480,6 +480,7 @@ &main_i2c2 { &sdhci0 { status = "okay"; + non-removable; ti,driver-strength-ohm = <50>; disable-wp; bootph-all; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 20d1437f253d..7d249fd04561 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -453,6 +453,7 @@ &main_i2c2 { &sdhci0 { bootph-all; status = "okay"; + non-removable; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; From ef839ba8142f14513ba396a033110526b7008096 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 10:14:54 -0500 Subject: [PATCH 36/86] arm64: dts: ti: k3-am6*: Remove disable-wp for eMMC Remove disable-wp flag for eMMC nodes since this flag is only applicable to SD according to the binding doc (mmc/mmc-controller-common.yaml). For eMMC, this flag should be ignored but lets remove anyways to cleanup sdhci nodes. Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah Link: https://lore.kernel.org/r/20250429151454.4160506-4-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 - arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 - arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 - arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 - arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am69-sk.dts | 1 - 10 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 55ed418c023b..e5be92aa1218 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -381,7 +381,6 @@ serial_flash: flash@0 { &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - disable-wp; non-removable; bootph-all; status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 1c8b4d13fb49..72b09f9c69d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -835,7 +835,6 @@ &sdhci0 { non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - disable-wp; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 147d56b87984..0d4115590b9c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -338,7 +338,6 @@ serial_flash: flash@0 { &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - disable-wp; non-removable; bootph-all; status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 22be41d46eb5..c65ada5a22ab 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -634,7 +634,6 @@ &sdhci0 { non-removable; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - disable-wp; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ab06cc42b4f2..b89b7a779bcc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -482,7 +482,6 @@ &sdhci0 { status = "okay"; non-removable; ti,driver-strength-ohm = <50>; - disable-wp; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 7d249fd04561..c6c8a9d17fb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -456,7 +456,6 @@ &sdhci0 { non-removable; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - disable-wp; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index f8ec40523254..5c6197ba842e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -597,7 +597,6 @@ &sdhci0 { status = "okay"; non-removable; ti,driver-strength-ohm = <50>; - disable-wp; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index aa7139cc8a92..c30425960398 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -456,7 +456,6 @@ &sdhci0 { bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; - disable-wp; }; /* diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index ae842b85b70d..12af6cb7f65c 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -50,5 +50,4 @@ &sdhci0 { bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; - disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index b85227052f97..f28375629739 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -940,7 +940,6 @@ &main_sdhci0 { status = "okay"; non-removable; ti,driver-strength-ohm = <50>; - disable-wp; }; &main_sdhci1 { From 1159f911435b9371575d9956bb5aef579265d29a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:36 +0530 Subject: [PATCH 37/86] arm64: dts: ti: k3-am64-main: Switch to 64-bit address space for PCIe0 The PCIe0 instance of PCIe in AM64 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d872a624601c..c7e5da37486a 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1036,7 +1036,7 @@ pcie0_rc: pcie@f102000 { reg = <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1054,8 +1054,8 @@ pcie0_rc: pcie@f102000 { vendor-id = <0x104c>; device-id = <0xb010>; msi-map = <0x0 &gic_its 0x0 0x10000>; - ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; status = "disabled"; }; From 46e3d7d7048872ffb90aa25e360b975dc1c3e28b Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:37 +0530 Subject: [PATCH 38/86] arm64: dts: ti: k3-j7200-main: Switch to 64-bit address space for PCIe1 The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index dbb000657377..5ce5f0a3d6f5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -764,7 +764,7 @@ pcie1_rc: pcie@2910000 { reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -783,8 +783,8 @@ pcie1_rc: pcie@2910000 { device-id = <0xb00f>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; From 1025003a1e068a25b35e1dbb39cad18e23278c0f Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:38 +0530 Subject: [PATCH 39/86] arm64: dts: ti: k3-j721e: Add ranges for PCIe0 DAT1 and PCIe1 DAT1 The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit address space of the respective PCIe Controllers. Hence, update the ranges to include them. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index a7f2f52f42f7..b6e22c242951 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -126,6 +126,8 @@ cbass_main: bus@100000 { <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ From f0f78192d3b3b3c3c935de0d681e7bf2117bbb13 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:39 +0530 Subject: [PATCH 40/86] arm64: dts: ti: k3-j721e-main: Switch to 64-bit address space for PCIe0 and PCIe1 The PCIe0 and PCIe1 instances of PCIe in J721E SoC support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index d7263ad43163..5bd0d36bf33e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -961,7 +961,7 @@ pcie0_rc: pcie@2900000 { reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -979,8 +979,8 @@ pcie0_rc: pcie@2900000 { device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -990,7 +990,7 @@ pcie1_rc: pcie@2910000 { reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1008,8 +1008,8 @@ pcie1_rc: pcie@2910000 { device-id = <0xb00d>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; From 5a765365c689b90ea81f651a43bc30cd9c9c4ed8 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:40 +0530 Subject: [PATCH 41/86] arm64: dts: ti: k3-j721s2-main: Switch to 64-bit address space for PCIe1 The PCIe1 instance of PCIe in J721S2 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-6-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index c0c2b95d4652..5071271c5a5c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1399,7 +1399,7 @@ pcie1_rc: pcie@2910000 { reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; + <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1417,8 +1417,8 @@ pcie1_rc: pcie@2910000 { device-id = <0xb013>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; From 0fde00328cf8245bf498349a696ba22d6a4a1916 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:41 +0530 Subject: [PATCH 42/86] arm64: dts: ti: k3-j722s-main: Switch to 64-bit address space for PCIe0 The PCIe0 instance of PCIe in J722S SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-7-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 562dfbdf449d..78d7e800b311 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -98,10 +98,10 @@ pcie0_rc: pcie@f102000 { reg = <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; interrupt-names = "link_state"; interrupts = ; From b1f9ec6545c6423e106f0aeddc3b8651b5ad116c Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 17:30:42 +0530 Subject: [PATCH 43/86] arm64: dts: ti: k3-j784s4-j742s2-main-common: Switch to 64-bit address space for PCIe0 and PCIe1 The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422120042.3746004-8-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 1fc0a11c5ab4..484f8e6930ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 { reg = <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1073,8 +1073,8 @@ pcie0_rc: pcie@2900000 { device-id = <0xb012>; msi-map = <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; @@ -1084,7 +1084,7 @@ pcie1_rc: pcie@2910000 { reg = <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names = "link_state"; interrupts = ; @@ -1102,8 +1102,8 @@ pcie1_rc: pcie@2910000 { device-id = <0xb012>; msi-map = <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status = "disabled"; }; From 9bfebd8750a06f5f8bf16ac58eb7deb638686d07 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 18:02:17 +0530 Subject: [PATCH 44/86] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE0 node The ACSPCIE0 module on TI's J784S4 SoC is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Add the device-tree node for the same. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422123218.3788223-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 484f8e6930ab..363d68fec387 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -126,6 +126,11 @@ audio_refclk1: clock@82e4 { assigned-clock-parents = <&k3_clks 157 63>; #clock-cells = <0>; }; + + acspcie0_proxy_ctrl: clock-controller@1a090 { + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg = <0x1a090 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { From e3dfcf482d0787a5882f10a33daa4c1ec62b87d2 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 22 Apr 2025 18:02:18 +0530 Subject: [PATCH 45/86] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1 The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250422123218.3788223-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 2664f74a9c7a..fa656b7b13a1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -5,6 +5,9 @@ * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 */ + +#include + / { chosen { stdout-path = "serial2:115200n8"; @@ -1407,10 +1410,13 @@ &main_mcan4 { &pcie1_rc { status = "okay"; + clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; num-lanes = <2>; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie1_link>; phy-names = "pcie-phy"; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; }; &serdes1 { From cd156f8741e362f3e0b0282c4abc3d0d0fecda57 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:10 +0200 Subject: [PATCH 46/86] dt-bindings: arm: ti: Add Toradex Verdin AM62P Add toradex,verdin-am62p for Toradex Verdin AM62 SoM, its nonwifi and wifi variants, and the Toradex carrier board they may be mated in. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Signed-off-by: Francesco Dolcini Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250430102815.149162-2-francesco@dolcini.it Signed-off-by: Nishanth Menon --- .../devicetree/bindings/arm/ti/k3.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index a6d9fd0bcaba..bf6003d8fb76 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -76,6 +76,30 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62p-nonwifi-dahlia # Verdin AM62P Module on Dahlia + - toradex,verdin-am62p-nonwifi-dev # Verdin AM62P Module on Verdin Development Board + - toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy + - toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow + - toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia + - const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62p-wifi-dahlia # Verdin AM62P Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62p-wifi-dev # Verdin AM62P Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy + - toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow + - toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module + - const: toradex,verdin-am62p # Verdin AM62P Module + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: From 87f95ea316ac68598544d512a3750cd4a73b5683 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:11 +0200 Subject: [PATCH 47/86] arm64: dts: ti: Add Toradex Verdin AM62P Add support for Toradex Verdin AM62P computer on module which can be used on different carrier boards and for the Toradex Verdin Development Board carrier board. The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250430102815.149162-3-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62p-verdin-dev.dtsi | 245 +++ .../boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi | 15 + .../boot/dts/ti/k3-am62p-verdin-wifi.dtsi | 31 + arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 1404 +++++++++++++++++ .../dts/ti/k3-am62p5-verdin-nonwifi-dev.dts | 22 + .../boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts | 22 + 7 files changed, 1741 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index a48e7608de8b..0902fcd5d731 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -35,6 +35,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb # Common overlays for SK-AM62* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi new file mode 100644 index 000000000000..0679d76f31bd --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + carrier_eth_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&carrier_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + clock-names = "mclk"; + clocks = <&audio_refclk0>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&main_uart1 { + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..8e7019f00e65 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-nonwifi.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +/* SDIO on MSP 30, 31, 32, 33, 34, 35 */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi new file mode 100644 index 000000000000..04d3124b5e0f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-wifi.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +/* On-module Bluetooth */ +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + keep-power-in-suspend; + non-removable; + ti,fails-without-test-cd; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi new file mode 100644 index 000000000000..226398c37fa9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -0,0 +1,1404 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + can0 = &main_mcan0; + can1 = &mcu_mcan0; + eeprom0 = &som_eeprom; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c0; + i2c2 = &main_i2c1; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &som_rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart6; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + /* Verdin SD_1 Power Supply */ + reg_sd1_vmmc: regulator-sdhci1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&main_gpio0 47 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sd1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd_vsel>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_3_DSI */ + pinctrl_epwm0_b: main-epwm0b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ /* SODIMM 19 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm2_a: main-epwm2a-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0124, PIN_OUTPUT, 4) /* (J25) MMC2_SDCD.EHRPWM2_A */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_1 */ + pinctrl_epwm2_b: main-epwm2b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0128, PIN_OUTPUT, 4) /* (K25) MMC2_SDWP.EHRPWM2_B */ /* SODIMM 15 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_INPUT, 7) /* (P23) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0004, PIN_INPUT, 7) /* (N23) OSPI0_LBCLKO.GPIO0_1 */ /* SODIMM 252 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: main-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0008, PIN_INPUT, 7) /* (P22) OSPI0_DQS.GPIO0_2 */ /* SODIMM 66 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x000c, PIN_INPUT, 7) /* (L25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0010, PIN_INPUT, 7) /* (N24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0014, PIN_INPUT, 7) /* (N25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0030, PIN_INPUT, 7) /* (L24) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* Verdin MSP_37 as GPIO */ + pinctrl_msp37_gpio: main-gpio0-13-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0034, PIN_INPUT, 7) /* (L22) OSPI0_CSn2.GPIO0_13 */ /* SODIMM 174 - WiFi_W_WKUP_HOST# */ + >; + }; + + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: main-gpio0-14-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ /* SODIMM 244 */ + >; + }; + + pinctrl_sd_vsel: main-gpio0-21-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0054, PIN_INPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ /* PMIC_SD_VSEL */ + >; + }; + + pinctrl_tpm_extint: main-gpio0-25-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0064, PIN_INPUT, 7) /* (AA25) GPMC0_AD10.GPIO0_25 */ /* TPM_EXTINT# */ + >; + }; + + pinctrl_wifi_wkup_bt: main-gpio0-29-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0074, PIN_INPUT, 7) /* (AB24) GPMC0_AD14.GPIO0_29 */ /* WiFi_WKUP_BT# */ + >; + }; + + pinctrl_wifi_wkup_wlan: main-gpio0-30-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0078, PIN_INPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ /* WiFi_WKUP_WLAN# */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio0-31-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 161 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-32-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0084, PIN_INPUT, 7) /* (R25) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 157 */ + >; + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 7) /* (U24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + pinctrl_eth_int: main-gpio0-36-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ /* ETH_INT# */ + >; + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + >; + }; + + /* Verdin DSI_1_INT# */ + pinctrl_dsi1_int: main-gpio0-38-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 17 */ + >; + }; + + /* Verdin DSI_1_BLK_EN# */ + pinctrl_dsi1_bkl_en: main-gpio0-39-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ /* SODIMM 21 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-41-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 187 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-42-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 189 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-47-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c0, PIN_INPUT, 7) /* (AA23) VOUT0_DATA2.GPIO0_47 */ /* SODIMM 76 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c8, PIN_INPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00cc, PIN_INPUT, 7) /* (AD23) VOUT0_DATA5.GPIO0_50 */ /* SODIMM 218 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-51-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d0, PIN_INPUT, 7) /* (AC23) VOUT0_DATA6.GPIO0_51 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-52-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d4, PIN_INPUT, 7) /* (AE23) VOUT0_DATA7.GPIO0_52 */ /* SODIMM 222 */ + >; + }; + + /* Verdin MSP_36 as GPIO */ + pinctrl_msp36_gpio: main-gpio0-57-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00e8, PIN_INPUT, 7) /* (AD21) VOUT0_DATA12.GPIO0_57 */ /* SODIMM 172 - WiFi_BT_WKUP_HOST# */ + >; + }; + + pinctrl_wifi_sd_int: main-gpio0-59-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f0, PIN_INPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 */ /* WIFI_SD_INT */ + >; + }; + + pinctrl_wifi_spi_cs: main-gpio0-60-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f4, PIN_INPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 */ /* WIFI_SPI_CS# */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-16-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */ /* SODIMM 19 */ + >; + }; + + /* Verdin SD_1_CD# */ + pinctrl_sd1_cd: main-gpio1-48-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0240, PIN_INPUT, 7) /* (D23) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ + >; + }; + + /* Verdin MSP_29 as GPIO */ + pinctl_msp29_gpio: main-gpio1-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ /* SODIMM 154 */ + >; + }; + + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0254, PIN_INPUT, 7) /* (G22) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_main_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ /* SODIMM 14 */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_main_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ /* SODIMM 55 */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_main_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_main_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ /* SODIMM 22 */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_3/MSP_8 as CAN */ + pinctrl_main_mcan1: main-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ /* SODIMM 92 */ + AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ /* SODIMM 104 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ /* SODIMM 74 */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ /* SODIMM 78 */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ /* SODIMM 80 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ /* SODIMM 82 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ /* SODIMM 70 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ /* SODIMM 72 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ + AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ + AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT, 0) /* (L21) MMC2_DAT3 */ /* SODIMM 168, WiFi_SDIO_DATA3 */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ /* SODIMM 52 */ + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62PX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (L24) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ /* SODIMM 56 */ + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ /* SODIMM 58 */ + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ /* SODIMM 60 */ + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ /* SODIMM 62 */ + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ /* SODIMM 66 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ /* RGMII_RXD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ /* RGMII_RXD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ /* RGMII_RXD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ /* RGMII_RXD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ /* RGMII_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ /* RGMII_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ /* RGMII_TXD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ /* RGMII_TXD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ /* RGMII_TXD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ /* RGMII_TXD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ /* RGMII_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ /* RGMII_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ /* SODIMM 201 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ /* SODIMM 203 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ /* SODIMM 205 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ /* SODIMM 207 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ /* SODIMM 197 */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ /* SODIMM 221 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ /* SODIMM 219 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ /* SODIMM 217 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ /* SODIMM 215 */ + AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ /* SODIMM 213 */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* TPM SPI, Optional Module Specific SPI */ + pinctrl_main_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_INPUT, 0) /* (B21) SPI0_CLK */ /* TPM_SPI_CLK - SODIMM 148 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ /* TPM_SPI_MOSI - SODIMM 150 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ /* TPM_SPI_MISO - SODIMM 152 */ + AM62PX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D20) SPI0_CS0 */ /* TPM_SPI_CS */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_main_spi1: main-spi1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0020, PIN_INPUT, 1) /* (N22) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62PX_IOPAD(0x0024, PIN_OUTPUT, 1) /* (P21) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62PX_IOPAD(0x0028, PIN_INPUT, 1) /* (N20) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* Verdin SPI_1_CS */ + pinctrl_main_spi1_cs0: main-spi1-cs0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x001c, PIN_OUTPUT, 1) /* (N21) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + >; + }; + + /* Verdin I2S_1 MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 5) /* (Y23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ /* SODIMM 38 */ + >; + }; + + pinctrl_eth_clock: main-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (C25) EXT_REFCLK1.CLKOUT0 */ /* ETH_25MHz_CLK */ + >; + }; + + pinctrl_pmic_extint: main-system-extint-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f4, PIN_INPUT, 0) /* (C23) EXTINTn */ /* PMIC_EXTINT# */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ /* SODIMM 147 */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + >; + }; + + /* Verdin MSP 41, 42, 44 and 45 as UART */ + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b8, PIN_INPUT, 4) /* (AE24) VOUT0_DATA0.UART2_RXD */ /* SODIMM 192 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 4) /* (W23) VOUT0_DATA1.UART2_TXD */ /* SODIMM 190 */ + AM62PX_IOPAD(0x0104, PIN_INPUT, 4) /* (Y21) VOUT0_PCLK.UART2_CTSn */ /* SODIMM 184 */ + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 4) /* (W20) VOUT0_VSYNC.UART2_RTSn */ /* SODIMM 186 */ + >; + }; + + /* Bluetooth on WB SKUs */ + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d8, PIN_INPUT, 4) /* (AE22) VOUT0_DATA8.UART6_RXD */ /* WiFi_UART_RXD */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (AC22) VOUT0_DATA9.UART6_TXD */ /* WiFi_UART_TXD */ + AM62PX_IOPAD(0x00e4, PIN_INPUT, 4) /* (AE21) VOUT0_DATA11.UART6_CTSn */ /* WiFi_UART_CTS */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (W22) VOUT0_DATA10.UART6_RTSn */ /* WiFi_UART_RTS */ + >; + }; + + /* Verdin USB_2_EN */ + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: mcasp0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 0) /* (F24) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62PX_IOPAD(0x01a8, PIN_INPUT, 0) /* (F25) MCASP0_AFSX */ /* SODIMM 32 */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62PX_IOPAD(0x019c, PIN_INPUT, 0) /* (E24) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 2) /* (R24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: mdio0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ /* SODIMM 193 */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ /* SODIMM 191 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (E10) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (C10) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (B11) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D10) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (E11) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62PX_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D11) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ /* SODIMM 22 */ + AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_13/MSP_18 as CAN */ + pinctrl_mcu_mcan1: mcu-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ /* SODIMM 116 */ + AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ /* SODIMM 128 */ + >; + }; + + /* Verdin UART_4 */ + pinctrl_mcu_uart0: mcu-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* (B6) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (C8) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_wkup_i2c0: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (A13) WKUP_I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62PX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (C11) WKUP_I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_wkup_clkout0: wkup-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +/* Verdin I2S_1_MCLK */ +&audio_refclk0 { + assigned-clock-rates = <25000000>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>, <&pinctrl_eth_clock>; + assigned-clocks = <&k3_clks 157 36>; + assigned-clock-parents = <&k3_clks 157 38>; + assigned-clock-rates = <25000000>; + status = "disabled"; + + som_eth_phy: ethernet-phy@0 { + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&som_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm2_a>, <&pinctrl_epwm2_b>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", + "SODIMM_252", + "SODIMM_66", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "SODIMM_174", + "SODIMM_244", + "", + "", + "", + "", + "", + "", /* 20 */ + "PMIC_SD_VSEL", + "", + "", + "", + "TPM_EXTINT#", + "", + "", + "", + "WiFi_WKUP_BT#", + "WiFi_WKUP_WLAN#", /* 30 */ + "SODIMM_161", + "SODIMM_157", + "", + "", + "", + "ETH_INT#", + "", + "SODIMM_17", + "SODIMM_21", + "", /* 40 */ + "SODIMM_187", + "SODIMM_189", + "", + "", + "", + "", + "SODIMM_76", + "", + "SODIMM_216", + "SODIMM_218", /* 50 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "SODIMM_172", + "", + "WIFI_SD_INT", + "WIFI_SPI_CS#", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 90 */ + ""; + + verdin_pcie_1_reset_hog: pcie-1-reset-hog { + gpio-hog; + /* Verdin PCIE_1_RESET# (SODIMM 244) */ + gpios = <14 GPIO_ACTIVE_LOW>; + line-name = "PCIE_1_RESET#"; + output-low; + status = "disabled"; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_154", + "SODIMM_155", /* 50 */ + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c0>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c3>; + status = "disabled"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcan0>; + status = "disabled"; +}; + +/* TPM SPI, optional SPI on module specific pins */ +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_extint>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi1>, <&pinctrl_main_spi1_cs0>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + no-mmc-hs400; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd>; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_sd1_vmmc>; + vqmmc-supply = <®_sd1_vqmmc>; + ti,fails-without-test-cd; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb0 { + adp-disable; + usb-role-switch; + status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* On-module I2C - PMIC_I2C */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + som_gpio_expander: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SODIMM_256"; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_3v3: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3 (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+V_PMIC_LDO2 (PMIC LDO4)"; // +VDDR_CORE + }; + + ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + som_rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* Verdin (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + uart-has-rtscts; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..5794f650f751 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62P on Verdin Development Board"; + compatible = "toradex,verdin-am62p-nonwifi-dev", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts new file mode 100644 index 000000000000..bbc2770d5f5d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Verdin Development Board"; + compatible = "toradex,verdin-am62p-wifi-dev", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; From c98ac03937e24913f90efe16832bac6c22ada76f Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:12 +0200 Subject: [PATCH 48/86] arm64: dts: ti: am62p-verdin: Add dahlia Add support for Verdin AM62P mated with Verdin Dahlia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250430102815.149162-4-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62p-verdin-dahlia.dtsi | 228 ++++++++++++++++++ .../ti/k3-am62p5-verdin-nonwifi-dahlia.dts | 22 ++ .../dts/ti/k3-am62p5-verdin-wifi-dahlia.dts | 22 ++ 4 files changed, 274 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 0902fcd5d731..436f71f22ade 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -35,7 +35,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb # Common overlays for SK-AM62* family of boards diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi new file mode 100644 index 000000000000..ee3feac6ea5d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dahlia.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier +V1.8_SW"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + clocks = <&audio_refclk0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..1790e572eaa0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62P on Dahlia Board"; + compatible = "toradex,verdin-am62p-nonwifi-dahlia", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..12b57985f38e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Dahlia Board"; + compatible = "toradex,verdin-am62p-wifi-dahlia", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; From cfdd38cfeb87d2a69303f3cf1bbc57d404826b28 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:13 +0200 Subject: [PATCH 49/86] arm64: dts: ti: am62p-verdin: Add mallow Add support for Verdin AM62P mated with Verdin Mallow carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250430102815.149162-5-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62p-verdin-mallow.dtsi | 213 ++++++++++++++++++ .../ti/k3-am62p5-verdin-nonwifi-mallow.dts | 22 ++ .../dts/ti/k3-am62p5-verdin-wifi-mallow.dts | 22 ++ 4 files changed, 259 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 436f71f22ade..52e24a31793a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -37,8 +37,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-mallow.dtb # Common overlays for SK-AM62* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi new file mode 100644 index 000000000000..37c0b9da82da --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-mallow.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Mallow carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>; + + /* SODIMM 52 - USER_LED_1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - USER_LED_1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - USER_LED_2_RED */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - USER_LED_2_GREEN */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-0 = <&pinctrl_main_spi1>, + <&pinctrl_main_spi1_cs0>, + <&pinctrl_qspi1_cs2_gpio>; + cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&main_gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts new file mode 100644 index 000000000000..52823874eadc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-mallow.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin AM62P on Mallow Board"; + compatible = "toradex,verdin-am62p-nonwifi-mallow", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts new file mode 100644 index 000000000000..e35851451cd4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-mallow.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Mallow Board"; + compatible = "toradex,verdin-am62p-wifi-mallow", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; From b0a01514cd906bb90eb2c7589a69429bced7ba1d Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:14 +0200 Subject: [PATCH 50/86] arm64: dts: ti: am62p-verdin: Add yavia Add support for Verdin AM62P mated with Verdin Yavia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250430102815.149162-6-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62p-verdin-yavia.dtsi | 219 ++++++++++++++++++ .../dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts | 22 ++ .../dts/ti/k3-am62p5-verdin-wifi-yavia.dts | 22 ++ 4 files changed, 265 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 52e24a31793a..d719d5f57877 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -38,9 +38,11 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-mallow.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-mallow.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-yavia.dtb # Common overlays for SK-AM62* family of boards dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi new file mode 100644 index 000000000000..b7423a774dc5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-yavia.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..c27bda794b51 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62P on Yavia Board"; + compatible = "toradex,verdin-am62p-nonwifi-yavia", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..25e0842bc905 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Yavia Board"; + compatible = "toradex,verdin-am62p-wifi-yavia", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; From 441870bb81b22d4a3937caeb4b890a94b40c689d Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 30 Apr 2025 12:28:15 +0200 Subject: [PATCH 51/86] arm64: dts: ti: am62p-verdin: Add ivy Add support for Verdin AM62P mated with Verdin Ivy carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250430102815.149162-7-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62p-verdin-ivy.dtsi | 629 ++++++++++++++++++ .../dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts | 22 + .../boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts | 22 + 4 files changed, 675 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index d719d5f57877..3c3aa09a94b6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -37,10 +37,12 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-yavia.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi new file mode 100644 index 000000000000..317c8818f9ee --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Ivy carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +#include +#include +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + /* AIN1 Voltage w/o AIN1_MODE gpio control */ + ain1_voltage_unmanaged: voltage-divider-ain1 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc1 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN1 Current w/o AIN1_MODE gpio control */ + ain1_current_unmanaged: current-sense-shunt-ain1 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc1 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN1_MODE - SODIMM 216 */ + ain1_mode_mux_ctrl: mux-controller-0 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_5>; + #mux-control-cells = <0>; + mux-gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + }; + + ain1-voltage { + compatible = "io-channel-mux"; + channels = "ain1_voltage", ""; + io-channels = <&ain1_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain1-current { + compatible = "io-channel-mux"; + channels = "", "ain1_current"; + io-channels = <&ain1_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + /* AIN2 Voltage w/o AIN2_MODE gpio control */ + ain2_voltage_unmanaged: voltage-divider-ain2 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc2 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN2 Current w/o AIN2_MODE gpio control */ + ain2_current_unmanaged: current-sense-shunt-ain2 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc2 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN2_MODE - SODIMM 218 */ + ain2_mode_mux_ctrl: mux-controller-1 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_6>; + #mux-control-cells = <0>; + mux-gpios = <&main_gpio0 50 GPIO_ACTIVE_HIGH>; + }; + + ain2-voltage { + compatible = "io-channel-mux"; + channels = "ain2_voltage", ""; + io-channels = <&ain2_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-current { + compatible = "io-channel-mux"; + channels = "", "ain2_current"; + io-channels = <&ain2_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ivy_leds>; + + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_3v2_ain1: regulator-3v2-ain1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN1"; + }; + + reg_3v2_ain2: regulator-3v2-ain2 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN2"; + }; + + /* Ivy Power Supply Input Voltage */ + ivy-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&som_adc 7>; + full-ohms = <204700>; /* 200K + 4.7K */ + output-ohms = <4700>; + }; + + ivy-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&som_adc 6>; + full-ohms = <39000>; /* 27K + 12K */ + output-ohms = <12000>; + }; + + ivy-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&som_adc 5>; + full-ohms = <54000>; /* 27K + 27K */ + output-ohms = <27000>; + }; + + ivy-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&som_adc 4>; + full-ohms = <39000>; /* 12K + 27K */ + output-ohms = <27000>; + }; +}; + +&main_pmx0 { + pinctrl_ivy_leds: ivy-leds-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_INPUT, 7) /* (E24) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */ + AM62PX_IOPAD(0x01a4, PIN_INPUT, 7) /* (F24) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */ + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + carrier_eth_phy: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&carrier_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + gpio-line-names = + "", /* 0 */ + "", + "REL4", /* SODIMM 66 */ + "DIGI_1", /* SODIMM 56 */ + "DIGI_2", /* SODIMM 58 */ + "REL1", /* SODIMM 60 */ + "REL2", /* SODIMM 62 */ + "", + "", + "", + "", /* 10 */ + "", + "REL3", /* SODIMM 64 */ + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 90 */ + ""; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; + + ivy_adc1: adc@40 { + compatible = "ti,ads1119"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_7>; + interrupt-parent = <&main_gpio0>; + interrupts = <51 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain1>; + dvdd-supply = <®_3v2_ain1>; + vref-supply = <®_3v2_ain1>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN1 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN1 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; + + ivy_adc2: adc@41 { + compatible = "ti,ads1119"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; + interrupt-parent = <&main_gpio0>; + interrupts = <52 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain2>; + dvdd-supply = <®_3v2_ain2>; + vref-supply = <®_3v2_ain2>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN2 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN2 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-0 = <&pinctrl_main_spi1>, + <&pinctrl_main_spi1_cs0>, + <&pinctrl_gpio_1>, + <&pinctrl_gpio_4>; + cs-gpios = <0>, + <&mcu_gpio0 1 GPIO_ACTIVE_LOW>, + <&mcu_gpio0 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; + + fram@2 { + compatible = "fujitsu,mb85rs256", "atmel,at25"; + reg = <2>; + address-width = <16>; + size = <32768>; + spi-max-frequency = <33000000>; + pagesize = <1>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>; + gpio-line-names = + "", + "", + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + ""; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts new file mode 100644 index 000000000000..a777513f26ec --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-ivy.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin AM62P on Ivy Board"; + compatible = "toradex,verdin-am62p-nonwifi-ivy", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts new file mode 100644 index 000000000000..27467281bc3a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-ivy.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Ivy Board"; + compatible = "toradex,verdin-am62p-wifi-ivy", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; From 3a71cdfec94436079513d9adf4b1d4f7a7edd917 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 11:33:35 -0500 Subject: [PATCH 52/86] arm64: dts: ti: k3-am62-main: Set eMMC clock parent to default Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Acked-by: Udit Kumar Acked-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250429163337.15634-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 7d355aa73ea2..0c286f600296 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -552,8 +552,6 @@ sdhci0: mmc@fa10000 { power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 57 6>; - assigned-clock-parents = <&k3_clks 57 8>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; From 6af731c5de59cc4e7cce193d446f1fe872ac711b Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 11:33:36 -0500 Subject: [PATCH 53/86] arm64: dts: ti: k3-am62a-main: Set eMMC clock parent to default Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: d3ae4e8d8b6a ("arm64: dts: ti: k3-am62a-main: Add sdhci0 instance") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Acked-by: Udit Kumar Acked-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250429163337.15634-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index a1daba7b1fad..455ccc770f16 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -575,8 +575,6 @@ sdhci0: mmc@fa10000 { power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 57 6>; - assigned-clock-parents = <&k3_clks 57 8>; bus-width = <8>; mmc-hs200-1_8v; ti,clkbuf-sel = <0x7>; From 9c6b73fc72e19c449147233587833ce20f84b660 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 11:33:37 -0500 Subject: [PATCH 54/86] arm64: dts: ti: k3-am62p-j722s-common-main: Set eMMC clock parent to default Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Acked-by: Udit Kumar Acked-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250429163337.15634-4-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 7b65538110e8..fa55c43ca28d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -573,8 +573,6 @@ sdhci0: mmc@fa10000 { power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 57 2>; - assigned-clock-parents = <&k3_clks 57 4>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; From f55c9f087cc2e2252d44ffd9d58def2066fc176e Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 29 Apr 2025 12:30:08 -0500 Subject: [PATCH 55/86] arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0 For am65x, add missing ITAPDLYSEL values for Default Speed and High Speed SDR modes to sdhci0 node according to the device datasheet [0]. [0] https://www.ti.com/lit/gpn/am6548 Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez Reviewed-by: Moteen Shah Link: https://lore.kernel.org/r/20250429173009.33994-1-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 6d3c467d7038..b085e7361116 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -449,6 +449,8 @@ sdhci0: mmc@4f80000 { ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; ti,itap-del-sel-ddr52 = <0x0>; dma-coherent; status = "disabled"; From 90770c243c384ddde070099e37a3ef2f3b71ff8a Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Fri, 2 May 2025 21:55:36 +0530 Subject: [PATCH 56/86] arm64: dts: ti: k3-am62p5-sk: Add regulator nodes for AM62P Add regulator node for AM62P-SK VCC_3V3_MAIN is the output of LM5141-Q1, and it serves as an input to TPS22965DSGT which produces VCC_3V3_SYS [1] VCC_3V3_SYS servers as vin-supply for peripherals like CSI [1]. Link: https://www.ti.com/lit/zip/sprr487 [1] Reviewed-by: Devarsh Thakkar Signed-off-by: Rishikesh Donadkar Link: https://lore.kernel.org/r/20250502162539.322091-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index b89b7a779bcc..fa94f723aef0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -115,6 +115,28 @@ vddshv_sdio: regulator-3 { bootph-all; }; + vcc_3v3_main: regulator-4 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_main"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-5 { + /* output of TPS222965DSGT */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; From d44915df7592b27e3e8c8b3e87c03603e3b0103a Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Fri, 2 May 2025 21:55:37 +0530 Subject: [PATCH 57/86] arm64: dts: ti: k3-am62x: Add required voltage supplies for IMX219 The device tree overlay for the IMX219 sensor requires three voltage supplies to be defined: VANA (analog), VDIG (digital core), and VDDL (digital I/O) [1]. Add the corresponding voltage supply definitions in the overlay so that the same topography as dt-bindings is present in the DT overlay. Link: https://datasheets.raspberrypi.com/camera/camera-module-2-schematics.pdf [1] Reviewed-by: Devarsh Thakkar Signed-off-by: Rishikesh Donadkar Link: https://lore.kernel.org/r/20250502162539.322091-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso index dd090813a32d..149c59c07182 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso @@ -15,6 +15,33 @@ clk_imx219_fixed: imx219-xclk { #clock-cells = <0>; clock-frequency = <24000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; }; &main_i2c2 { @@ -40,6 +67,10 @@ ov5640: camera@10 { clocks = <&clk_imx219_fixed>; + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; + reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>; port { From 23a5409369b11e9174ba95ba8ddedcffacdf9529 Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Fri, 2 May 2025 21:55:38 +0530 Subject: [PATCH 58/86] arm64: dts: ti: k3-am62x: Add required voltage supplies for OV5640 The device tree overlay for OV5640 requires following voltage supplies as mentioned in the table 8-3 of the data-sheet [1]. AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Link: https://cdn.sparkfun.com/datasheets/Sensors/LightImaging/OV5640_datasheet.pdf Reviewed-by: Devarsh Thakkar Signed-off-by: Rishikesh Donadkar Link: https://lore.kernel.org/r/20250502162539.322091-4-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso index 7fc7c95f5cd5..fc77fc77fe0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -15,6 +15,33 @@ clk_ov5640_fixed: ov5640-xclk { #clock-cells = <0>; clock-frequency = <12000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; }; &main_i2c2 { @@ -40,6 +67,11 @@ ov5640: camera@3c { clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; port { From 30ce5f163e4fb81d1467b15ecc508889be7eabca Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Fri, 2 May 2025 21:55:39 +0530 Subject: [PATCH 59/86] arm64: dts: ti: k3-am62x: Add required voltage supplies for TEVI-OV5640 The device tree overlay for TEVI-OV5640 requires following voltage supplies as mentioned in the power section [1] AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the DT overlay. Link: https://www.technexion.com/wp-content/uploads/2023/09/product-brief_tevi-ov5640.pdf Signed-off-by: Rishikesh Donadkar Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20250502162539.322091-5-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso index b6bfdfbbdd98..fe3bc29632fa 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -15,6 +15,33 @@ clk_ov5640_fixed: ov5640-xclk { #clock-cells = <0>; clock-frequency = <24000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + }; }; &main_i2c2 { @@ -40,6 +67,11 @@ ov5640: camera@3c { clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>; port { From a5da12f37b8532b7ea9196ae7c7927a535883194 Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Tue, 6 May 2025 10:22:24 +0530 Subject: [PATCH 60/86] arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for OV5640 The device tree overlay for OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20250506045225.1246873-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- .../ti/k3-am625-beagleplay-csi2-ov5640.dtso | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso index 3b4643b7d19c..000305c9e366 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso @@ -15,6 +15,33 @@ clk_ov5640_fixed: ov5640-xclk { #clock-cells = <0>; clock-frequency = <12000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; }; &main_gpio0 { @@ -39,6 +66,10 @@ ov5640: camera@3c { clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; + port { csi2_cam0: endpoint { remote-endpoint = <&csi2rx0_in_sensor>; From cabe662bd54b37deb7ebf0a4dbaabc7812fa411c Mon Sep 17 00:00:00 2001 From: Rishikesh Donadkar Date: Tue, 6 May 2025 10:22:25 +0530 Subject: [PATCH 61/86] arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for TEVI-OV5640 The device tree overlay for TEVI-OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20250506045225.1246873-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon --- .../k3-am625-beagleplay-csi2-tevi-ov5640.dtso | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso index 81a2763d43c6..8a7a9ece08af 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso @@ -15,6 +15,33 @@ clk_ov5640_fixed: ov5640-xclk { #clock-cells = <0>; clock-frequency = <24000000>; }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; }; &main_gpio0 { @@ -39,6 +66,10 @@ ov5640: camera@3c { clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + port { csi2_cam0: endpoint { remote-endpoint = <&csi2rx0_in_sensor>; From 5bb1949ffa021056b389393c5edb22abba5372c3 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Fri, 2 May 2025 17:03:15 -0500 Subject: [PATCH 62/86] arm64: dts: ti: k3-am62: Add ATCM and BTCM cbass ranges Add cbass ranges for ATCM and BTCM on am62x device, without these, remoteproc driver fails to probe and attach to the DM r5 core and IPC communication is broken. Signed-off-by: Judith Mendez Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index bfb55ca11323..59f6dff552ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -86,7 +86,9 @@ cbass_main: bus@f0000 { /* Wakeup Domain Range */ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ cbass_mcu: bus@4000000 { bootph-all; @@ -103,7 +105,9 @@ cbass_wakeup: bus@b00000 { #size-cells = <2>; ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; From 5722117235aca01893dbda9dbc7e4790b0b9d43c Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:16 -0500 Subject: [PATCH 63/86] arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F node AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Tested-by: Daniel Schultz Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 9b8a1f85aa15..6549b7efa656 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -106,6 +106,31 @@ wkup_rti0: watchdog@2b000000 { status = "reserved"; }; + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + resets = <&k3_reset 121 1>; + firmware-name = "am62-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible = "ti,j7200-vtm"; reg = <0x00 0xb00000 0x00 0x400>, From 7f321892dc53015e29cd1055231727b8cdc24923 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:17 -0500 Subject: [PATCH 64/86] arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node AM62A SoCs have a single R5F core in the MCU voltage domain. Add the R5FSS node with the child node for core0 in MCU voltage domain .dtsi file. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Tested-by: Daniel Schultz Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-4-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 9ed9d703ff24..ee961ced7208 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -174,4 +174,29 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + resets = <&k3_reset 9 1>; + firmware-name = "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + }; + }; }; From f0623719c2a612cbb9d5927fc5ffef9b54a12fb7 Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 2 May 2025 17:03:18 -0500 Subject: [PATCH 65/86] arm64: dts: ti: k3-am62a-wakeup: Add R5F device node AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Tested-by: Daniel Schultz Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-5-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index b2c8f5351743..259ae6ebbfb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -103,6 +103,31 @@ wkup_rti0: watchdog@2b000000 { status = "reserved"; }; + wkup_r5fss0: r5fss@78000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible = "ti,am62-r5f"; + reg = <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names = "atcm", "btcm"; + resets = <&k3_reset 121 1>; + firmware-name = "am62a-wkup-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible = "ti,j7200-vtm"; reg = <0x00 0xb00000 0x00 0x400>, From 56f13d79430f8faa27943e376ac25aca0836ee93 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Fri, 2 May 2025 17:03:19 -0500 Subject: [PATCH 66/86] arm64: dts: ti: k3-am62a-main: Add C7xv device node AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Tested-by: Daniel Schultz Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-6-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 455ccc770f16..63e097ddf988 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1121,6 +1121,18 @@ vpu: video-codec@30210000 { power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + c7x_0: dsp@7e000000 { + compatible = "ti,am62a-c7xv-dsp"; + reg = <0x00 0x7e000000 0x00 0x00100000>; + reg-names = "l2sram"; + resets = <&k3_reset 208 1>; + firmware-name = "am62a-c71_0-fw"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <208>; + ti,sci-proc-ids = <0x04 0xff>; + status = "disabled"; + }; + e5010: jpeg-encoder@fd20000 { compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; reg = <0x00 0xfd20000 0x00 0x100>, From 77c29ebe76d80174d5735b61edd3c95e32a75d2e Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 2 May 2025 17:03:20 -0500 Subject: [PATCH 67/86] arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processors For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Reviewed-by: Beleswar Padhi Reviewed-by: Jai Luthra Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-7-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 96 +++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index c65ada5a22ab..59a872413bab 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -52,6 +52,42 @@ linux,cma { linux,cma-default; }; + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -63,12 +99,6 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; opp-table { @@ -782,3 +812,57 @@ &epwm1 { pinctrl-0 = <&main_epwm1_pins_default>; status = "okay"; }; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; From b05a6c145001e99348a2fe33958be912f4eb8d4d Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Fri, 2 May 2025 17:03:21 -0500 Subject: [PATCH 68/86] arm64: dts: ti: k3-am62p5-sk: Enable IPC with remote processors For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-8-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 50 ++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index fa94f723aef0..83c37de7d338 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,6 +49,30 @@ reserved-memory { #size-cells = <2>; ranges; + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -58,12 +82,6 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; vmain_pd: regulator-0 { @@ -688,6 +706,26 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; From 8fb034b8402ead1028ed63394a177947b1450fcd Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:22 -0500 Subject: [PATCH 69/86] arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processors For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-9-jm@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 34 ++++++++++++++++--- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index c6c8a9d17fb5..ee8337bfbbfd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -70,6 +70,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 { no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -82,11 +94,6 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; }; leds { @@ -495,10 +502,17 @@ cpsw3g_phy0: ethernet-phy@0 { }; &mailbox0_cluster0 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &mcu_m4fss { @@ -508,6 +522,16 @@ &mcu_m4fss { status = "okay"; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + &usbss0 { bootph-all; status = "okay"; From 2a473854bea16de7d3502ae2cd1ba4481eb632e9 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:23 -0500 Subject: [PATCH 70/86] arm64: dts: ti: k3-am62a7-sk: Reserve main_timer2 for C7x DSP C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-10-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 59a872413bab..1f1a27667bcb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -702,6 +702,11 @@ &main_uart1 { status = "reserved"; }; +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; + &usbss0 { status = "okay"; ti,vbus-divider; From b4ec77305c2645ce96c4a13aca0c375815e06672 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:24 -0500 Subject: [PATCH 71/86] arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSP The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-11-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 1f1a27667bcb..b27759026014 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -871,3 +871,8 @@ &c7x_0 { <&c7x_0_memory_region>; status = "okay"; }; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; From e4b55d85024f806c9b364d498e0ebbc74d76d77d Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Fri, 2 May 2025 17:03:25 -0500 Subject: [PATCH 72/86] arm64: dts: ti: k3-am64: Reserve timers used by MCU FW AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses main domain timers as tick timers in these firmwares. Hence keep them as reserved in the Linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250502220325.3230653-12-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 20 ++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 5c6197ba842e..e01866372293 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -795,6 +795,26 @@ &mcu_m4fss { status = "okay"; }; +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &serdes_ln_ctrl { idle-states = ; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 33e421ec18ab..1deaa0be0085 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -710,6 +710,26 @@ &mcu_m4fss { status = "okay"; }; +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */ From 3df22a8622fafa1c5a0dba93c207f66f48366858 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 30 Apr 2025 09:43:43 -0500 Subject: [PATCH 73/86] arm64: dts: ti: k3-am62-main: Add PRUSS-M node Add the DT node for the PRUSS-M processor subsystem that is present on the K3 AM62x SoCs. The K3 AM62x family of SoC has one PRUSS-M instance and it has two Programmable Real-Time Units (PRU0 and PRU1). Signed-off-by: Kishon Vijay Abraham I [ Judith: Fix pruss_iclk id for pruss_coreclk_mux ] Signed-off-by: Judith Mendez Tested-by: Daniel Schultz Reviewed-by: Beleswar Padhi Acked-by: Hari Nagalla Link: https://lore.kernel.org/r/20250430144343.972234-1-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 90 ++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 0c286f600296..50ba7dcff80f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -1077,6 +1077,96 @@ dphy0: phy@30110000 { status = "disabled"; }; + pruss: pruss@30040000 { + compatible = "ti,am625-pruss"; + reg = <0x00 0x30040000 0x00 0x80000>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x30040000 0x80000>; + + pruss_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", "shrdram2"; + }; + + pruss_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + pruss_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 81 0>, /* pruss_core_clk */ + <&k3_clks 81 14>; /* pruss_iclk */ + assigned-clocks = <&pruss_coreclk_mux>; + assigned-clock-parents = <&k3_clks 81 14>; + }; + + pruss_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 81 3>, /* pruss_iep_clk */ + <&pruss_coreclk_mux>; /* pruss_coreclk_mux */ + assigned-clocks = <&pruss_iepclk_mux>; + assigned-clock-parents = <&pruss_coreclk_mux>; + }; + }; + }; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru0: pru@34000 { + compatible = "ti,am625-pru"; + reg = <0x34000 0x3000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru0-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <16 2 2>; + interrupt-names = "vring"; + }; + + pru1: pru@38000 { + compatible = "ti,am625-pru"; + reg = <0x38000 0x3000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am62x-pru1-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <18 3 3>; + interrupt-names = "vring"; + }; + }; + gpmc0: memory-controller@3b000000 { compatible = "ti,am64-gpmc"; power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; From 8a6650dafaede08c565f88ee1d5920a498941f76 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Mon, 28 Apr 2025 12:07:14 +0100 Subject: [PATCH 74/86] arm64: dts: ti: k3-am62: New GPU binding details Use the new compatible string and power domain name as introduced in commit 2c01d9099859 ("dt-bindings: gpu: img: Future-proofing enhancements"). Reviewed-by: Randolph Sapp Signed-off-by: Matt Coster Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-1-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 50ba7dcff80f..9e0b6eee9ac7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -689,12 +689,14 @@ ospi0: spi@fc40000 { }; gpu: gpu@fd00000 { - compatible = "ti,am62-gpu", "img,img-axe"; + compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", + "img,img-rogue"; reg = <0x00 0x0fd00000 0x00 0x20000>; clocks = <&k3_clks 187 0>; clock-names = "core"; interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "a"; }; cpsw3g: ethernet@8000000 { From ed6f779e213070572e53e9801e4a6e510d7bc208 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Mon, 28 Apr 2025 12:07:15 +0100 Subject: [PATCH 75/86] arm64: dts: ti: k3-j721s2: Add GPU node The J721S2 binding is based on the TI downstream binding in commit 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from HTML docs, while the interrupt index comes from the TRM[4] (appendix "J721S2_Appendix_20241106_Public.xlsx", "Interrupts (inputs)", "GPU_BXS464_WRAP0_GPU_SS_0_OS_IRQ_OUT_0"). [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html [4]: https://www.ti.com/lit/zip/spruj28 (revision E) Reviewed-by: Randolph Sapp Signed-off-by: Matt Coster Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-2-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 5071271c5a5c..83cf0adb2cb7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -2053,4 +2053,18 @@ watchdog8: watchdog@23f0000 { /* reserved for MAIN_R5F1_1 */ status = "reserved"; }; + + gpu: gpu@4e20000000 { + compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg = <0x4e 0x20000000 0x00 0x80000>; + clocks = <&k3_clks 130 1>; + clock-names = "core"; + assigned-clocks = <&k3_clks 130 1>; + assigned-clock-rates = <800000000>; + interrupts = ; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names = "a", "b"; + dma-coherent; + }; }; From 6b8deb2ff0d31848c43a73f6044e69ba9276b3ec Mon Sep 17 00:00:00 2001 From: Prasanth Babu Mantena Date: Wed, 7 May 2025 10:37:01 +0530 Subject: [PATCH 76/86] arm64: dts: ti: k3-j721e-common-proc-board: Enable OSPI1 on J721E J721E SoM has MT25QU512AB Serial NOR flash connected to OSPI1 controller. Enable ospi1 node in device tree. Fixes: 73676c480b72 ("arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level") Signed-off-by: Prasanth Babu Mantena Link: https://lore.kernel.org/r/20250507050701.3007209-1-p-mantena@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e3d0ef6913b2..45311438315f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -573,6 +573,7 @@ &usb1 { &ospi1 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + status = "okay"; flash@0 { compatible = "jedec,spi-nor"; From 8785b579d431b2a76a64f105328434d3c543debf Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 6 May 2025 04:41:33 -0700 Subject: [PATCH 77/86] arm64: dts: ti: k3-am62a: Enable CPU freq throttling on thermal alert Enable throttling down the CPU frequency when an alert temperature threshold (lower than the critical threshold) is reached. Signed-off-by: Daniel Schultz Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20250506114134.3514899-1-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi | 57 ++++++++++++++++++-- arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 4 ++ 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi index c7486fb2a5b4..3aa127157d24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi @@ -12,12 +12,29 @@ main0_thermal: main0-thermal { thermal-sensors = <&wkup_vtm0 0>; trips { + main0_alert: main0-alert { + temperature = <115000>; + hysteresis = <2000>; + type = "passive"; + }; + main0_crit: main0-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&main0_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; main1_thermal: main1-thermal { @@ -26,25 +43,59 @@ main1_thermal: main1-thermal { thermal-sensors = <&wkup_vtm0 1>; trips { + main1_alert: main1-alert { + temperature = <115000>; + hysteresis = <2000>; + type = "passive"; + }; + main1_crit: main1-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&main1_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 2>; + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; trips { + main2_alert: main2-alert { + temperature = <115000>; + hysteresis = <2000>; + type = "passive"; + }; + main2_crit: main2-crit { temperature = <125000>; /* milliCelsius */ hysteresis = <2000>; /* milliCelsius */ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&main2_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index 6c99221beb6b..b6e5eee99370 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -50,6 +50,7 @@ cpu0: cpu@0 { next-level-cache = <&L2_0>; operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -66,6 +67,7 @@ cpu1: cpu@1 { next-level-cache = <&L2_0>; operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ cpu2: cpu@2 { next-level-cache = <&L2_0>; operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -98,6 +101,7 @@ cpu3: cpu@3 { next-level-cache = <&L2_0>; operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; + #cooling-cells = <2>; }; }; From 625e540cee2cfa0e514e0c8fb929fe2893e6d3bf Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 6 May 2025 04:41:34 -0700 Subject: [PATCH 78/86] arm64: dts: ti: k3-am62x-phyboard-lyra-gpio-fan: Update cooling maps Rename 'main0_thermal_trip0' to a more descriptive name that includes 'fan', as the current name is too generic for a fan control trip point. Move the fan to a new cooling map to avoid overwriting the passive trip point used for CPU frequency throttling when this overlay is enabled. Also, add the fan to the existing cooling map. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20250506114134.3514899-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- .../dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso index f0b2fd4165a7..1fd0aaff3193 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso @@ -33,7 +33,7 @@ AM62X_IOPAD(0x0a4, PIN_OUTPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ &thermal_zones { main0_thermal: main0-thermal { trips { - main0_thermal_trip0: main0-thermal-trip { + main0_fan: main0-fan { temperature = <65000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "active"; @@ -42,7 +42,17 @@ main0_thermal_trip0: main0-thermal-trip { cooling-maps { map0 { - trip = <&main0_thermal_trip0>; + trip = <&main0_alert>; + cooling-device = + <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&main0_fan>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; From c0fa0aaa69ac3a8d242fc12cdad8cfc4b8fcdba6 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 7 May 2025 00:00:05 -0700 Subject: [PATCH 79/86] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors For every remote processor, set up dedicated memory regions and associate the required mailbox channels. Allocate two memory areas per remote core: one 1MB region for vring shared buffers, and another for external memory used by the remote processor for its resource table and trace buffer. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov Reviewed-by: Andrew Davis Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20250507070008.1231611-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-phycore-som.dtsi | 35 +++++++++++++++---- 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index e5be92aa1218..10e6b5c08619 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -64,6 +64,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 { no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -75,12 +87,6 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0x00c00000>; - no-map; - }; }; vcc_5v0_som: regulator-vcc-5v0-som { @@ -240,10 +246,17 @@ cpsw3g_phy1: ethernet-phy@1 { }; &mailbox0_cluster0 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &main_pktdma { @@ -385,3 +398,13 @@ &sdhci0 { bootph-all; status = "okay"; }; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; From 8dd0ac27fcd1ea64612d1f2392c69bc2648aef2e Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 7 May 2025 00:00:06 -0700 Subject: [PATCH 80/86] arm64: dts: ti: k3-am62a-phycore-som: Enable Co-processors For every remote processor, set up dedicated memory regions and associate the required mailbox channels. Allocate two memory areas per remote core: one 1MB region for vring shared buffers, and another for external memory used by the remote processor for its resource table and trace buffer. Signed-off-by: Daniel Schultz Reviewed-by: Andrew Davis Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20250507070008.1231611-3-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 96 +++++++++++++++++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 0d4115590b9c..a39efcbeebff 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -59,6 +59,42 @@ linux,cma { linux,cma-default; }; + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -70,12 +106,6 @@ secure_ddr: optee@9e800000 { alignment = <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; vcc_5v0_som: regulator-vcc-5v0-som { @@ -170,6 +200,13 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */ }; }; +&c7x_0 { + mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; @@ -200,6 +237,33 @@ &fss { status = "okay"; }; +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -315,6 +379,16 @@ &main_pktdma { bootph-all; }; +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -342,3 +416,13 @@ &sdhci0 { bootph-all; status = "okay"; }; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; From 5d0727b0537f3e5c3c457ead700a5cdb1ee7eaf7 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 7 May 2025 00:00:07 -0700 Subject: [PATCH 81/86] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Daniel Schultz Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20250507070008.1231611-4-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index a39efcbeebff..7554ab2368e5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -379,6 +379,11 @@ &main_pktdma { bootph-all; }; +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + &mcu_r5fss0 { status = "okay"; }; From f71fb19f36044290669dccfc31d1de6ef3d0eed6 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 7 May 2025 00:00:08 -0700 Subject: [PATCH 82/86] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 for C7x DSP C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Daniel Schultz Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20250507070008.1231611-5-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 7554ab2368e5..5dc5d2cb20cc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -384,6 +384,11 @@ &main_rti4 { status = "reserved"; }; +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; + &mcu_r5fss0 { status = "okay"; }; From 9bb89ec393e368cf26a65c04cfd4a14851368df0 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 9 May 2025 14:49:08 +0530 Subject: [PATCH 83/86] arm64: dts: ti: j722s-evm: Add DT nodes for power regulators Add device tree nodes for two regulators on the J722S-EVM. VSYS_3V3 is the output of LM5141-Q1, and it serves as an input to TPS22990 which produces VSYS_3V3_EXP [1]. VSYS_3V3_EXP serves as vin-supply to CSI RPI Connectors. Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar [1]: https://www.ti.com/lit/zip/sprr495 Link: https://lore.kernel.org/r/20250509091911.2442934-2-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 34b9d190800e..2213993acbc9 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -141,6 +141,17 @@ vsys_5v0: regulator-vsys5v0 { regulator-boot-on; }; + vsys_3v3: regulator-vsys3v3 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + vdd_mmc1: regulator-mmc1 { /* TPS22918DBVR */ compatible = "regulator-fixed"; @@ -153,6 +164,17 @@ vdd_mmc1: regulator-mmc1 { bootph-all; }; + vsys_3v3_exp: regulator-TPS22990 { + /* output of TPS22990 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3_exp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + vdd_sd_dv: regulator-TLV71033 { compatible = "regulator-gpio"; regulator-name = "tlv71033"; From 2e8861103a08e4220e99b673ab247aff108ddef5 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 9 May 2025 14:49:09 +0530 Subject: [PATCH 84/86] arm64: dts: ti: j722s-evm: Add MUX to control CSI2RX J722S EVM has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model mux so that an overlay can control the mux state according to connected cameras. Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250509091911.2442934-3-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 2213993acbc9..a47852fdca70 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -266,6 +266,20 @@ transceiver2: can-phy2 { max-bitrate = <5000000>; standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>; }; + + csi01_mux: mux-controller-0 { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + + csi23_mux: mux-controller-1 { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp1 7 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { From 646bcbcbdfad22818d32c8771583844aab4e05dd Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Fri, 9 May 2025 14:49:10 +0530 Subject: [PATCH 85/86] arm64: dts: ti: k3-j722s-evm: Add overlay for quad IMX219 RPi v2 Camera (IMX219) is an 8MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad IMX219 RPI camera v2 modules on J722S EVM Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250509091911.2442934-4-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 5 + ...k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso | 329 ++++++++++++++++++ 2 files changed, 334 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 3c3aa09a94b6..281a282fcbfb 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb @@ -225,6 +226,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \ @@ -263,6 +266,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ @@ -288,5 +292,6 @@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721e-evm-pcie0-ep += -@ DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ +DTC_FLAGS_k3-j722s-evm += -@ DTC_FLAGS_k3-j784s4-evm += -@ DTC_FLAGS_k3-j742s2-evm += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso new file mode 100644 index 000000000000..4107ef8c7b74 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for 4 x RPi Camera V2.1 on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) /* (R22) GPIO0_15 */ + >; + }; + + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) /* (R26) GPIO0_17 */ + >; + }; + + cam2_reset_pins_default: cam2-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) /* (T25) GPIO0_19 */ + >; + }; + + cam3_reset_pins_default: cam3-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) /* (T21) GPIO0_21 */ + >; + }; +}; + +&{/} { + clk_imx219_fixed: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; +}; + +&csi01_mux { + idle-state = <1>; +}; + +&csi23_mux { + idle-state = <1>; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_0: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_1: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + imx219_2: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + reset-gpios = <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + imx219_3: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + + VANA-supply = <®_2p8v>; + VDIG-supply = <®_1p8v>; + VDDL-supply = <®_1p2v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +}; From 6a9d340b1f9910f0f88e0819c464938b91610765 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Fri, 9 May 2025 14:49:11 +0530 Subject: [PATCH 86/86] arm64: dts: ti: k3-j722s-evm: Add overlay for TEVI OV5640 TechNexion TEVI OV5640 camera is a 5MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad TEVI OV5640 modules on J722S EVM. Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250509091911.2442934-5-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-j722s-evm-csi2-quad-tevi-ov5640.dtso | 323 ++++++++++++++++++ 2 files changed, 327 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 281a282fcbfb..c6171de9fe88 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb @@ -228,6 +229,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo +k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \ k3-j784s4-j742s2-evm-usb0-type-a.dtbo k3-j784s4-evm-pcie0-pcie1-ep-dtbs := k3-j784s4-evm.dtb \ @@ -267,6 +270,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ + k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso new file mode 100644 index 000000000000..575113d7b481 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-csi2-quad-tevi-ov5640.dtso @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for 4 x TEVI OV5640 MIPI Camera module on J722S-EVM board. + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x03c, PIN_OUTPUT, 7) /* (R22) GPIO0_15 */ + >; + }; + + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x044, PIN_OUTPUT, 7) /* (R26) GPIO0_17 */ + >; + }; + + cam2_reset_pins_default: cam2-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x04c, PIN_OUTPUT, 7) /* (T25) GPIO0_19 */ + >; + }; + + cam3_reset_pins_default: cam3-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x054, PIN_OUTPUT, 7) /* (T21) GPIO0_21 */ + >; + }; +}; + +&{/} { + clk_ov5640_fixed: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3_exp>; + regulator-always-on; + }; +}; + +&csi01_mux { + idle-state = <1>; +}; + +&csi23_mux { + idle-state = <1>; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_0: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_1: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&pca9543_1 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ov5640_2: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam2_reset_pins_default>; + + reset-gpios = <&main_gpio0 19 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam2: endpoint { + remote-endpoint = <&csi2rx2_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ov5640_3: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_3p3v>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam3_reset_pins_default>; + + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam3: endpoint { + remote-endpoint = <&csi2rx3_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx2_in_sensor: endpoint { + remote-endpoint = <&csi2_cam2>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx3_in_sensor: endpoint { + remote-endpoint = <&csi2_cam3>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx2 { + status = "okay"; +}; + +&dphy2 { + status = "okay"; +}; + +&ti_csi2rx3 { + status = "okay"; +}; + +&dphy3 { + status = "okay"; +};