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Merge branch '20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com' into HEAD

Browse Source 
Merge the Nord video and camera clock controller bindings from a topic
branch, in order to use these in DeviceTree source.
This commit is contained in:
Bjorn Andersson 2026-09-24 09:46:25 -05:00
commit 17769685ec
4 changed files with 174 additions and 0 deletions
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2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
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@ -19,6 +19,7 @@ description: |
include/dt-bindings/clock/qcom,hawi-camcc.h
include/dt-bindings/clock/qcom,kaanapali-camcc.h
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,nord-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
@ -32,6 +33,7 @@ properties:
- qcom,hawi-camcc
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,nord-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc

2
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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@ -19,6 +19,7 @@ description: |
include/dt-bindings/clock/qcom,hawi-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,maili-videocc.h
include/dt-bindings/clock/qcom,nord-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@ -31,6 +32,7 @@ properties:
- qcom,hawi-videocc
- qcom,kaanapali-videocc
- qcom,maili-videocc
- qcom,nord-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc

167
include/dt-bindings/clock/qcom,nord-camcc.h Normal file
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@ -0,0 +1,167 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H
/* CAM_CC clocks */
#define CAM_CC_CAMNOC_DCD_XO_CLK 0
#define CAM_CC_CAMNOC_NRT_AXI_CLK 1
#define CAM_CC_CAMNOC_RT_AXI_CLK 2
#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3
#define CAM_CC_CAMNOC_XO_CLK 4
#define CAM_CC_CCI_0_CLK 5
#define CAM_CC_CCI_0_CLK_SRC 6
#define CAM_CC_CCI_1_CLK 7
#define CAM_CC_CCI_1_CLK_SRC 8
#define CAM_CC_CCI_2_CLK 9
#define CAM_CC_CCI_2_CLK_SRC 10
#define CAM_CC_CCI_3_CLK 11
#define CAM_CC_CCI_3_CLK_SRC 12
#define CAM_CC_CCI_4_CLK 13
#define CAM_CC_CCI_4_CLK_SRC 14
#define CAM_CC_CCU_FAST_AHB_CLK 15
#define CAM_CC_CORE_AHB_CLK 16
#define CAM_CC_CPHY_RX_CLK_SRC 17
#define CAM_CC_CSI0PHYTIMER_CLK 18
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 19
#define CAM_CC_CSI1PHYTIMER_CLK 20
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 21
#define CAM_CC_CSI2PHYTIMER_CLK 22
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 23
#define CAM_CC_CSI3PHYTIMER_CLK 24
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 25
#define CAM_CC_CSI4PHYTIMER_CLK 26
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27
#define CAM_CC_CSID_CLK 28
#define CAM_CC_CSID_CLK_SRC 29
#define CAM_CC_CSID_CSIPHY_RX_CLK 30
#define CAM_CC_CSIPHY0_CLK 31
#define CAM_CC_CSIPHY1_CLK 32
#define CAM_CC_CSIPHY2_CLK 33
#define CAM_CC_CSIPHY3_CLK 34
#define CAM_CC_CSIPHY4_CLK 35
#define CAM_CC_FAST_AHB_CLK_SRC 36
#define CAM_CC_GDSC_CLK 37
#define CAM_CC_ICP_0_AHB_CLK 38
#define CAM_CC_ICP_0_CLK 39
#define CAM_CC_ICP_0_CLK_SRC 40
#define CAM_CC_ICP_1_AHB_CLK 41
#define CAM_CC_ICP_1_CLK 42
#define CAM_CC_ICP_1_CLK_SRC 43
#define CAM_CC_IFE_0_MAIN_CLK 44
#define CAM_CC_IFE_0_MAIN_CLK_SRC 45
#define CAM_CC_IFE_0_MAIN_FAST_AHB_CLK 46
#define CAM_CC_IFE_0_PCP_CLK 47
#define CAM_CC_IFE_0_PCP_FAST_AHB_CLK 48
#define CAM_CC_IFE_0_SCALAR_CLK 49
#define CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK 50
#define CAM_CC_IFE_0_TMC_CLK 51
#define CAM_CC_IFE_0_TMC_FAST_AHB_CLK 52
#define CAM_CC_IFE_1_MAIN_CLK 53
#define CAM_CC_IFE_1_MAIN_CLK_SRC 54
#define CAM_CC_IFE_1_MAIN_FAST_AHB_CLK 55
#define CAM_CC_IFE_1_PCP_CLK 56
#define CAM_CC_IFE_1_PCP_FAST_AHB_CLK 57
#define CAM_CC_IFE_1_SCALAR_CLK 58
#define CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK 59
#define CAM_CC_IFE_1_TMC_CLK 60
#define CAM_CC_IFE_1_TMC_FAST_AHB_CLK 61
#define CAM_CC_IFE_2_MAIN_CLK 62
#define CAM_CC_IFE_2_MAIN_CLK_SRC 63
#define CAM_CC_IFE_2_MAIN_FAST_AHB_CLK 64
#define CAM_CC_IFE_2_PCP_CLK 65
#define CAM_CC_IFE_2_PCP_FAST_AHB_CLK 66
#define CAM_CC_IFE_2_SCALAR_CLK 67
#define CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK 68
#define CAM_CC_IFE_2_TMC_CLK 69
#define CAM_CC_IFE_2_TMC_FAST_AHB_CLK 70
#define CAM_CC_IFE_LITE_AHB_CLK 71
#define CAM_CC_IFE_LITE_CLK 72
#define CAM_CC_IFE_LITE_CLK_SRC 73
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 74
#define CAM_CC_IFE_LITE_CSID_CLK 75
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 76
#define CAM_CC_IPE_0_AHB_CLK 77
#define CAM_CC_IPE_0_CLK 78
#define CAM_CC_IPE_0_CLK_SRC 79
#define CAM_CC_IPE_0_FAST_AHB_CLK 80
#define CAM_CC_IPE_1_AHB_CLK 81
#define CAM_CC_IPE_1_CLK 82
#define CAM_CC_IPE_1_CLK_SRC 83
#define CAM_CC_IPE_1_FAST_AHB_CLK 84
#define CAM_CC_PLL0 85
#define CAM_CC_PLL0_OUT_EVEN 86
#define CAM_CC_PLL0_OUT_ODD 87
#define CAM_CC_PLL2 88
#define CAM_CC_PLL2_OUT_EVEN 89
#define CAM_CC_PLL3 90
#define CAM_CC_PLL3_OUT_EVEN 91
#define CAM_CC_PLL4 92
#define CAM_CC_PLL4_OUT_EVEN 93
#define CAM_CC_PLL5 94
#define CAM_CC_PLL5_OUT_EVEN 95
#define CAM_CC_PLL6 96
#define CAM_CC_PLL6_OUT_EVEN 97
#define CAM_CC_QDSS_DEBUG_CLK 98
#define CAM_CC_QDSS_DEBUG_CLK_SRC 99
#define CAM_CC_QDSS_DEBUG_XO_CLK 100
#define CAM_CC_QUP_AHBM_CLK 101
#define CAM_CC_QUP_AHBM_CLK_SRC 102
#define CAM_CC_QUP_CORE_2X_CLK 103
#define CAM_CC_QUP_CORE_2X_CLK_SRC 104
#define CAM_CC_QUP_CORE_2X_DIV_CLK_SRC 105
#define CAM_CC_QUP_CORE_CLK 106
#define CAM_CC_QUP_SE_CLK 107
#define CAM_CC_QUP_SE_CLK_SRC 108
#define CAM_CC_QUP_SLEEP_CLK 109
#define CAM_CC_SFE_LITE_0_CLK 110
#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 111
#define CAM_CC_SFE_LITE_1_CLK 112
#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 113
#define CAM_CC_SFE_LITE_2_CLK 114
#define CAM_CC_SFE_LITE_2_FAST_AHB_CLK 115
#define CAM_CC_SLEEP_CLK 116
#define CAM_CC_SLEEP_CLK_SRC 117
#define CAM_CC_SLOW_AHB_CLK_SRC 118
#define CAM_CC_SM_OBS_CLK 119
#define CAM_CC_TOP_AHB_CLK 120
#define CAM_CC_TOP_FAST_AHB_CLK 121
#define CAM_CC_TOP_IFE_0_CLK 122
#define CAM_CC_TOP_IFE_1_CLK 123
#define CAM_CC_TOP_IFE_2_CLK 124
#define CAM_CC_TOP_IFE_LITE_CLK 125
#define CAM_CC_TOP_IPE_0_CLK 126
#define CAM_CC_TOP_IPE_1_CLK 127
#define CAM_CC_TOP_QUP_AHBM_CLK 128
#define CAM_CC_TOP_SFE_LITE_0_CLK 129
#define CAM_CC_TOP_SFE_LITE_1_CLK 130
#define CAM_CC_TOP_SFE_LITE_2_CLK 131
#define CAM_CC_TPG_CSIPHY_RX_CLK 132
#define CAM_CC_XO_CLK_SRC 133
/* CAM_CC power domains */
#define CAM_CC_IFE_0_GDSC 0
#define CAM_CC_IFE_1_GDSC 1
#define CAM_CC_IFE_2_GDSC 2
#define CAM_CC_IPE_0_GDSC 3
#define CAM_CC_IPE_1_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
/* CAM_CC resets */
#define CAM_CC_CCU_BCR 0
#define CAM_CC_ICP_0_BCR 1
#define CAM_CC_ICP_1_BCR 2
#define CAM_CC_IFE_0_BCR 3
#define CAM_CC_IFE_1_BCR 4
#define CAM_CC_IFE_2_BCR 5
#define CAM_CC_IPE_0_BCR 6
#define CAM_CC_IPE_1_BCR 7
#define CAM_CC_QDSS_DEBUG_BCR 8
#define CAM_CC_SFE_LITE_0_BCR 9
#define CAM_CC_SFE_LITE_1_BCR 10
#define CAM_CC_SFE_LITE_2_BCR 11
#endif

3
include/dt-bindings/clock/qcom,nord-nwgcc.h
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@ -65,5 +65,8 @@
#define NW_GCC_GPU_2_BCR 6
#define NW_GCC_GPU_BCR 7
#define NW_GCC_VIDEO_BCR 8
#define NW_GCC_VIDEO_AXI0_CLK_ARES 9
#define NW_GCC_VIDEO_AXI0C_CLK_ARES 10
#define NW_GCC_VIDEO_AXI1_CLK_ARES 11
#endif