diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 6e4288d38321..f22dea937088 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -940,17 +940,30 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_max_freq_mode(struct ufs_hba *hba)
 	}
 
 	switch (max_freq) {
+	case 403000000:
+		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 403, 16);
+		break;
 	case 300000000:
 		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 300, 12);
 		break;
+	case 201500000:
+		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 202, 8);
+		break;
 	case 150000000:
 		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150, 6);
 		break;
+	case 100000000:
+		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 100, 4);
+		break;
 	default:
 		err = -EINVAL;
 		break;
 	}
 
+	if (err) {
+		dev_err(hba->dev, "unipro max_freq=%u entry missing\n", max_freq);
+		dump_stack();
+	}
 	return err;
 }
 
@@ -2078,6 +2091,7 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba)
 		hba->caps |= UFSHCD_CAP_CLK_GATING |
 			UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
 		hba->caps |= UFSHCD_CAP_WB_EN;
+		hba->caps |= UFSHCD_CAP_CLK_SCALING;
 	}
 
 	hba->caps |= UFSHCD_CAP_CRYPTO;
@@ -3514,8 +3528,12 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
 	case 75000000:
 		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75, 3);
 		break;
+	case 100000000:
+		err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 100, 4);
+		break;
 	default:
 		err = -EINVAL;
+		dev_err(hba->dev, "unipro curr_freq=%u entry missing\n", curr_freq);
 		break;
 	}
 
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 779802c328b6..755102b977a0 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -218,7 +218,7 @@ enum ufs_qcom_phy_init_type {
 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_OFFSET_V4	0x10
 
 #define PA_VS_CORE_CLK_40NS_CYCLES	0x9007
-#define PA_VS_CORE_CLK_40NS_CYCLES_MASK	0xF
+#define PA_VS_CORE_CLK_40NS_CYCLES_MASK	0x3F
 
 #define DL_VS_CLK_CFG		0xA00B
 #define DL_VS_CLK_CFG_MASK	0x3FF