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arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags

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The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-3-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Wadim Egorov 2025-03-05 09:55:35 +01:00 committed by Vignesh Raghavendra
parent 2285ea3f80
commit 17141e9cab
2 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
View File

@ -27,6 +27,7 @@ aliases {
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-all;
};
reserved_memory: reserved-memory {
@ -138,6 +139,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
>;
bootph-all;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
@ -156,6 +158,7 @@ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
>;
bootph-all;
};
eeprom_wp_pins_default: eeprom-wp-default-pins {
@ -175,6 +178,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
bootph-all;
};
ospi0_pins_default: ospi0-default-pins {
@ -191,6 +195,7 @@ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
bootph-all;
};
rtc_pins_default: rtc-defaults-pins {
@ -210,6 +215,7 @@ &cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
bootph-all;
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
@ -221,12 +227,14 @@ cpsw3g_phy1: ethernet-phy@1 {
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
bootph-all;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
status = "okay";
};
@ -272,6 +280,7 @@ &main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
bootph-all;
eeprom@50 {
compatible = "atmel,24c32";
@ -336,6 +345,10 @@ vdda_1v8: ldo1 {
};
};
&main_pktdma {
bootph-all;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
@ -383,6 +396,7 @@ serial_flash: flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
bootph-all;
};
};
@ -392,6 +406,7 @@ &sdhci0 {
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
bootph-all;
};
&tscadc0 {

5
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
View File

@ -171,6 +171,7 @@ vcc_3v3_mmc: regulator-sd {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
bootph-all;
};
};
@ -275,6 +276,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
>;
bootph-all;
};
main_spi0_pins_default: main-spi0-default-pins {
@ -291,6 +293,7 @@ main_uart0_pins_default: main-uart0-default-pins {
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@ -413,6 +416,7 @@ &main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
bootph-all;
};
&main_uart1 {
@ -429,6 +433,7 @@ &sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
no-1-8-v;
bootph-all;
};
&serdes0 {