github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-24 23:22:31 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

- add power domains support for mt8195

Browse Source 
- disable ACP on mt8192
 
 mt8186:
 - add support for power domains
 - add mmsys and mutex support needed for DRM
 - add reset control based on mmsys subsystem
 - add pmic wrapper
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmId5EgXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH4gEg/+LL7XjcWZlD8GwTfJEeZjgk3c
 06rne1kKh0mm9+VEIHOp0RsMf4IdbHwCbAt3xMMcdOqAxh4oaKchCE0fPS2d+mdA
 2qZaysEBxG6RTs/wY9fS1/diGge3OroW3CuS0cv6mKh7acY9tLW5/VRvvgcOzSrT
 eJYGQqpXg4VfUJ41e7otIhj32Npltby9lBlo8Z5kF3Vy7yYAUEZvNrGrp0pmwkvM
 UJRlCZFoSGAfoijJfpH38vixi+qWYOiAhulweT01VhtIVYHjh+BmoQc4jZ8A7fhW
 ttzlrbYPELRD0eu6/zfdokXWVwZjkqB5HoumN7IaYW+ZUEY6iYhy9J+Ir9qpG82D
 Z4cbk4JMc6uEAjTdu6njdzlBukw80oXOo6nCyPa+xvniNWPoYTHN5JZaNWig4taC
 5i9diVBuwkOdYARKSFqxk1FuvvSDh+8QP9hNiomXZrPUjZgilXDQ2CncKFr70CNM
 iCQqCiHNpzaVEMxBkve2aU9kKc5qVixrLAqh/VOwpUln66aE1Ug51zzdAAkalyQv
 di6iZMRFy+pL3oNPFWAKv0Z0yowBj/QDFBZiOc/SqXrrNpHNDfMVPcSdZVtjSBXD
 DqPxPFRHaqV/+eFHc9xyvgKMMbg2xYsZXVrleyQWiXck0x2mshw3hIcghGpkPGDB
 w+b5BPpeewE49tamKJs=
 =KUFa
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmId8OYACgkQmmx57+YA
 GNlaoA//cdGz81n8HG8zy1DpprypmbUCJv6SruIF1XE2ewOgZ486IiA0H1yYdSD5
 kDmok9SDjFM+WmqxoGUQl5hcNH67ThD/5rxgKgrIpi4kpfhgjbhYLJ9PGjZSAc4v
 9zW+l48WDYxHmq7xhsCgsC6BoimM3MHwJTA3crMzXqtG3PecrLtnMS6EAaX/Uoub
 Vw7HW8v7PAeO9xx4tBV+c65jYDmmcBm21iv9EptEUOgK06OhjyH6KoQjFwGpg/tb
 uEDehYDK5pULc9U2322sfRJ0b0LpD/+yJMREITe9XYuHX+4akqVEscEVvnwh/j+1
 PXwwtGOnVMk/5TLaLUQy181x4soXG+8uBVbitHpZVCfmRvel6fAbnfgAxyf7sYy/
 Kdbp1apVnQ7nDeW/rhR7glNrJSUN+R2uBbfmXPyU+MOoPG+1Ckz6YR4VrjKx0M/N
 K7qkqwJxp7TkuFJXzqWi58apyHqBdM9LzsyroRjk8FqeDC60T6RQDhJXuXDpDp58
 na4WDaS5expzgWpGiJwrm2MfT0rbI9X7pyGRcCPY6kVwtnLX84npVal6ZbS8jCwp
 KRO13i/ZzZj9ZNlOhANgYodedW4dO/tyW39xMIzYrQ+5QjQ8IvD+DFnv50F1DzON
 5IbTBTDS1B07dIikIb9FFLrGZL/bqEtafg9kGsYfypmXfVPf3FY=
 =G//M
 -----END PGP SIGNATURE-----

Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

- add power domains support for mt8195
- disable ACP on mt8192

mt8186:
- add support for power domains
- add mmsys and mutex support needed for DRM
- add reset control based on mmsys subsystem
- add pmic wrapper

* tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  soc: mediatek: pm-domains: Move power status offset to power domain data
  soc: mediatek: pm-domains: Remove unused macro
  soc: mediatek: pm-domains: Add wakeup capacity support in power domain
  dt-bindings: power: Add MT8195 power domains

Link: https://lore.kernel.org/r/16a53482-5a8c-e95e-8cd4-b8304f110987@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-03-01 11:09:41 +01:00
commit 16e769e2ae
19 changed files with 1559 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -29,6 +29,7 @@ properties:
- mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8365-mmsys
- const: syscon

3
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
View File

@ -26,7 +26,9 @@ properties:
- mediatek,mt8167-power-controller
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8186-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
'#power-domain-cells':
const: 1
@ -64,6 +66,7 @@ patternProperties:
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
maxItems: 1
clocks:

1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@ -27,6 +27,7 @@ Required properties in pwrap device node.
"mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs
"mediatek,mt8186-pwrap" for MT8186 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC

16
drivers/soc/mediatek/mt8167-pm-domains.h
View File

@ -18,6 +18,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "mm",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -30,6 +32,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
@ -38,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
@ -46,6 +52,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "mfg_async",
.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
.bp_infracfg = {
@ -57,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "mfg_2d",
.sta_mask = MT8167_PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -64,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -71,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
@ -85,8 +99,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
static const struct scpsys_soc_data mt8167_scpsys_data = {
.domains_data = scpsys_domain_data_mt8167,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
};
#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */

22
drivers/soc/mediatek/mt8173-pm-domains.h
View File

@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "vdec",
.sta_mask = PWR_STATUS_VDEC,
.ctl_offs = SPM_VDE_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "venc",
.sta_mask = PWR_STATUS_VENC,
.ctl_offs = SPM_VEN_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -29,6 +33,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = SPM_ISP_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
},
@ -36,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "mm",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = SPM_DIS_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -47,6 +55,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "venc_lt",
.sta_mask = PWR_STATUS_VENC_LT,
.ctl_offs = SPM_VEN2_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -54,6 +64,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "audio",
.sta_mask = PWR_STATUS_AUDIO,
.ctl_offs = SPM_AUDIO_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -61,6 +73,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "usb",
.sta_mask = PWR_STATUS_USB,
.ctl_offs = SPM_USB_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "mfg_async",
.sta_mask = PWR_STATUS_MFG_ASYNC,
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
.caps = MTK_SCPD_DOMAIN_SUPPLY,
@ -77,6 +93,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "mfg_2d",
.sta_mask = PWR_STATUS_MFG_2D,
.ctl_offs = SPM_MFG_2D_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
},
@ -84,6 +102,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
.bp_infracfg = {
@ -98,8 +118,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
static const struct scpsys_soc_data mt8173_scpsys_data = {
.domains_data = scpsys_domain_data_mt8173,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
};
#endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */

32
drivers/soc/mediatek/mt8183-pm-domains.h
View File

@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "audio",
.sta_mask = PWR_STATUS_AUDIO,
.ctl_offs = 0x0314,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
},
@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = 0x032c,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
.bp_infracfg = {
@ -33,6 +37,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "mfg_async",
.sta_mask = PWR_STATUS_MFG_ASYNC,
.ctl_offs = 0x0334,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
},
@ -40,6 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = 0x0338,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_DOMAIN_SUPPLY,
@ -48,6 +56,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "mfg_core0",
.sta_mask = BIT(7),
.ctl_offs = 0x034c,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -55,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "mfg_core1",
.sta_mask = BIT(20),
.ctl_offs = 0x0310,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -62,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "mfg_2d",
.sta_mask = PWR_STATUS_MFG_2D,
.ctl_offs = 0x0348,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -75,6 +89,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "disp",
.sta_mask = PWR_STATUS_DISP,
.ctl_offs = 0x030c,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -94,6 +110,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "cam",
.sta_mask = BIT(25),
.ctl_offs = 0x0344,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = {
@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "isp",
.sta_mask = PWR_STATUS_ISP,
.ctl_offs = 0x0308,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(9, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = {
@ -140,6 +160,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "vdec",
.sta_mask = BIT(31),
.ctl_offs = 0x0300,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_smi = {
@ -153,6 +175,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "venc",
.sta_mask = PWR_STATUS_VENC,
.ctl_offs = 0x0304,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.bp_smi = {
@ -166,6 +190,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "vpu_top",
.sta_mask = BIT(26),
.ctl_offs = 0x0324,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -193,6 +219,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "vpu_core0",
.sta_mask = BIT(27),
.ctl_offs = 0x33c,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = {
@ -211,6 +239,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
.name = "vpu_core1",
.sta_mask = BIT(28),
.ctl_offs = 0x0340,
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.bp_infracfg = {
@ -230,8 +260,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
static const struct scpsys_soc_data mt8183_scpsys_data = {
.domains_data = scpsys_domain_data_mt8183,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
.pwr_sta_offs = 0x0180,
.pwr_sta2nd_offs = 0x0184
};
#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */

115
drivers/soc/mediatek/mt8186-mmsys.h Normal file
View File

@ -0,0 +1,115 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
#define __SOC_MEDIATEK_MT8186_MMSYS_H
#define MT8186_MMSYS_OVL_CON 0xF04
#define MT8186_MMSYS_OVL0_CON_MASK 0x3
#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
#define MT8186_OVL0_GO_BLEND BIT(0)
#define MT8186_OVL0_GO_BG BIT(1)
#define MT8186_OVL0_2L_GO_BLEND BIT(2)
#define MT8186_OVL0_2L_GO_BG BIT(3)
#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
#define MT8186_DISP_OVL0_MOUT_EN 0xF18
#define MT8186_OVL0_MOUT_EN_MASK 0xF
#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
#define MT8186_DITHER0_MOUT_EN_MASK 0xF
#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
#define MT8186_DISP_RDMA0_SEL_IN 0xF28
#define MT8186_RDMA0_SEL_IN_MASK 0xF
#define MT8186_RDMA0_FROM_OVL0 0
#define MT8186_RDMA0_FROM_OVL0_2L 2
#define MT8186_DISP_DSI0_SEL_IN 0xF30
#define MT8186_DSI0_SEL_IN_MASK 0xF
#define MT8186_DSI0_FROM_RDMA0 0
#define MT8186_DSI0_FROM_DITHER0 1
#define MT8186_DSI0_FROM_RDMA1 2
#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
#define MT8186_RDMA1_MOUT_EN_MASK 0xF
#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
#define MT8186_DISP_RDMA1_SEL_IN 0xF40
#define MT8186_RDMA1_SEL_IN_MASK 0xF
#define MT8186_RDMA1_FROM_OVL0 0
#define MT8186_RDMA1_FROM_OVL0_2L 2
#define MT8186_RDMA1_FROM_DITHER0 3
#define MT8186_DISP_DPI0_SEL_IN 0xF44
#define MT8186_DPI0_SEL_IN_MASK 0xF
#define MT8186_DPI0_FROM_RDMA1 0
#define MT8186_DPI0_FROM_DITHER0 1
#define MT8186_DPI0_FROM_RDMA0 2
#define MT8186_MMSYS_SW0_RST_B 0x160
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0
},
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND
},
{
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L
},
{
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1
},
};
#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */

344
drivers/soc/mediatek/mt8186-pm-domains.h Normal file
View File

@ -0,0 +1,344 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8186-power.h>
/*
* MT8186 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
[MT8186_POWER_DOMAIN_MFG0] = {
.name = "mfg0",
.sta_mask = BIT(2),
.ctl_offs = 0x308,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8186_POWER_DOMAIN_MFG1] = {
.name = "mfg1",
.sta_mask = BIT(3),
.ctl_offs = 0x30c,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_MFG2] = {
.name = "mfg2",
.sta_mask = BIT(4),
.ctl_offs = 0x310,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_MFG3] = {
.name = "mfg3",
.sta_mask = BIT(5),
.ctl_offs = 0x314,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_SSUSB] = {
.name = "ssusb",
.sta_mask = BIT(20),
.ctl_offs = 0x9F0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8186_POWER_DOMAIN_SSUSB_P1] = {
.name = "ssusb_p1",
.sta_mask = BIT(19),
.ctl_offs = 0x9F4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8186_POWER_DOMAIN_DIS] = {
.name = "dis",
.sta_mask = BIT(21),
.ctl_offs = 0x354,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
},
},
[MT8186_POWER_DOMAIN_IMG] = {
.name = "img",
.sta_mask = BIT(13),
.ctl_offs = 0x334,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_IMG2] = {
.name = "img2",
.sta_mask = BIT(14),
.ctl_offs = 0x338,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_IPE] = {
.name = "ipe",
.sta_mask = BIT(15),
.ctl_offs = 0x33C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_CAM] = {
.name = "cam",
.sta_mask = BIT(23),
.ctl_offs = 0x35C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_CAM_RAWA] = {
.name = "cam_rawa",
.sta_mask = BIT(24),
.ctl_offs = 0x360,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_CAM_RAWB] = {
.name = "cam_rawb",
.sta_mask = BIT(25),
.ctl_offs = 0x364,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = BIT(18),
.ctl_offs = 0x348,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_VDEC] = {
.name = "vdec",
.sta_mask = BIT(16),
.ctl_offs = 0x340,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_WPE] = {
.name = "wpe",
.sta_mask = BIT(0),
.ctl_offs = 0x3F8,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
MT8186_TOP_AXI_PROT_EN_2_SET,
MT8186_TOP_AXI_PROT_EN_2_CLR,
MT8186_TOP_AXI_PROT_EN_2_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
MT8186_TOP_AXI_PROT_EN_2_SET,
MT8186_TOP_AXI_PROT_EN_2_CLR,
MT8186_TOP_AXI_PROT_EN_2_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_CONN_ON] = {
.name = "conn_on",
.sta_mask = BIT(1),
.ctl_offs = 0x304,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
MT8186_TOP_AXI_PROT_EN_1_SET,
MT8186_TOP_AXI_PROT_EN_1_CLR,
MT8186_TOP_AXI_PROT_EN_1_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
MT8186_TOP_AXI_PROT_EN_SET,
MT8186_TOP_AXI_PROT_EN_CLR,
MT8186_TOP_AXI_PROT_EN_STA),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8186_POWER_DOMAIN_CSIRX_TOP] = {
.name = "csirx_top",
.sta_mask = BIT(6),
.ctl_offs = 0x318,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_ADSP_AO] = {
.name = "adsp_ao",
.sta_mask = BIT(17),
.ctl_offs = 0x9FC,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_ADSP_INFRA] = {
.name = "adsp_infra",
.sta_mask = BIT(10),
.ctl_offs = 0x9F8,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8186_POWER_DOMAIN_ADSP_TOP] = {
.name = "adsp_top",
.sta_mask = BIT(31),
.ctl_offs = 0x3E4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
.bp_infracfg = {
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
MT8186_TOP_AXI_PROT_EN_3_SET,
MT8186_TOP_AXI_PROT_EN_3_CLR,
MT8186_TOP_AXI_PROT_EN_3_STA),
BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
MT8186_TOP_AXI_PROT_EN_3_SET,
MT8186_TOP_AXI_PROT_EN_3_CLR,
MT8186_TOP_AXI_PROT_EN_3_STA),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
};
static const struct scpsys_soc_data mt8186_scpsys_data = {
.domains_data = scpsys_domain_data_mt8186,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),
};
#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */

44
drivers/soc/mediatek/mt8192-pm-domains.h
View File

@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "audio",
.sta_mask = BIT(21),
.ctl_offs = 0x0354,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -28,6 +30,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = 0x0304,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
.bp_infracfg = {
@ -50,6 +54,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg0",
.sta_mask = BIT(2),
.ctl_offs = 0x0308,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -57,6 +63,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg1",
.sta_mask = BIT(3),
.ctl_offs = 0x030c,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -82,6 +90,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg2",
.sta_mask = BIT(4),
.ctl_offs = 0x0310,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -89,6 +99,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg3",
.sta_mask = BIT(5),
.ctl_offs = 0x0314,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -96,6 +108,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg4",
.sta_mask = BIT(6),
.ctl_offs = 0x0318,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -103,6 +117,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg5",
.sta_mask = BIT(7),
.ctl_offs = 0x031c,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -110,6 +126,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mfg6",
.sta_mask = BIT(8),
.ctl_offs = 0x0320,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "disp",
.sta_mask = BIT(20),
.ctl_offs = 0x0350,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -146,6 +166,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "ipe",
.sta_mask = BIT(14),
.ctl_offs = 0x0338,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -163,6 +185,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "isp",
.sta_mask = BIT(12),
.ctl_offs = 0x0330,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -180,6 +204,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "isp2",
.sta_mask = BIT(13),
.ctl_offs = 0x0334,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -197,6 +223,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "mdp",
.sta_mask = BIT(19),
.ctl_offs = 0x034c,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -214,6 +242,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "venc",
.sta_mask = BIT(17),
.ctl_offs = 0x0344,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -231,6 +261,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "vdec",
.sta_mask = BIT(15),
.ctl_offs = 0x033c,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -248,6 +280,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "vdec2",
.sta_mask = BIT(16),
.ctl_offs = 0x0340,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -255,6 +289,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "cam",
.sta_mask = BIT(23),
.ctl_offs = 0x035c,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
@ -284,6 +320,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "cam_rawa",
.sta_mask = BIT(24),
.ctl_offs = 0x0360,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -291,6 +329,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "cam_rawb",
.sta_mask = BIT(25),
.ctl_offs = 0x0364,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -298,6 +338,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.name = "cam_rawc",
.sta_mask = BIT(26),
.ctl_offs = 0x0368,
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
@ -306,8 +348,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
static const struct scpsys_soc_data mt8192_scpsys_data = {
.domains_data = scpsys_domain_data_mt8192,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
.pwr_sta_offs = 0x016c,
.pwr_sta2nd_offs = 0x0170,
};
#endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */

613
drivers/soc/mediatek/mt8195-pm-domains.h Normal file
View File

@ -0,0 +1,613 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8195-power.h>
/*
* MT8195 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
[MT8195_POWER_DOMAIN_PCIE_MAC_P0] = {
.name = "pcie_mac_p0",
.sta_mask = BIT(11),
.ctl_offs = 0x328,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
MT8195_TOP_AXI_PROT_EN_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
.name = "pcie_mac_p1",
.sta_mask = BIT(12),
.ctl_offs = 0x32C,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
MT8195_TOP_AXI_PROT_EN_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_PHY] = {
.name = "pcie_phy",
.sta_mask = BIT(13),
.ctl_offs = 0x330,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = {
.name = "ssusb_pcie_phy",
.sta_mask = BIT(14),
.ctl_offs = 0x334,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_CSI_RX_TOP] = {
.name = "csi_rx_top",
.sta_mask = BIT(18),
.ctl_offs = 0x3C4,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_ETHER] = {
.name = "ether",
.sta_mask = BIT(3),
.ctl_offs = 0x344,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_ADSP] = {
.name = "adsp",
.sta_mask = BIT(10),
.ctl_offs = 0x360,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = BIT(8),
.ctl_offs = 0x358,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8195_POWER_DOMAIN_MFG0] = {
.name = "mfg0",
.sta_mask = BIT(1),
.ctl_offs = 0x300,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8195_POWER_DOMAIN_MFG1] = {
.name = "mfg1",
.sta_mask = BIT(2),
.ctl_offs = 0x304,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
MT8195_TOP_AXI_PROT_EN_1_SET,
MT8195_TOP_AXI_PROT_EN_1_CLR,
MT8195_TOP_AXI_PROT_EN_1_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG2] = {
.name = "mfg2",
.sta_mask = BIT(3),
.ctl_offs = 0x308,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG3] = {
.name = "mfg3",
.sta_mask = BIT(4),
.ctl_offs = 0x30C,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG4] = {
.name = "mfg4",
.sta_mask = BIT(5),
.ctl_offs = 0x310,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG5] = {
.name = "mfg5",
.sta_mask = BIT(6),
.ctl_offs = 0x314,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG6] = {
.name = "mfg6",
.sta_mask = BIT(7),
.ctl_offs = 0x318,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VPPSYS0] = {
.name = "vppsys0",
.sta_mask = BIT(11),
.ctl_offs = 0x364,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS0] = {
.name = "vdosys0",
.sta_mask = BIT(13),
.ctl_offs = 0x36C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VPPSYS1] = {
.name = "vppsys1",
.sta_mask = BIT(12),
.ctl_offs = 0x368,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS1] = {
.name = "vdosys1",
.sta_mask = BIT(14),
.ctl_offs = 0x370,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_DP_TX] = {
.name = "dp_tx",
.sta_mask = BIT(16),
.ctl_offs = 0x378,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_EPD_TX] = {
.name = "epd_tx",
.sta_mask = BIT(17),
.ctl_offs = 0x37C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_HDMI_TX] = {
.name = "hdmi_tx",
.sta_mask = BIT(18),
.ctl_offs = 0x380,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_WPESYS] = {
.name = "wpesys",
.sta_mask = BIT(15),
.ctl_offs = 0x374,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDEC0] = {
.name = "vdec0",
.sta_mask = BIT(20),
.ctl_offs = 0x388,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VDEC1] = {
.name = "vdec1",
.sta_mask = BIT(21),
.ctl_offs = 0x38C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VDEC2] = {
.name = "vdec2",
.sta_mask = BIT(22),
.ctl_offs = 0x390,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = BIT(23),
.ctl_offs = 0x394,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VENC_CORE1] = {
.name = "venc_core1",
.sta_mask = BIT(24),
.ctl_offs = 0x398,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_IMG] = {
.name = "img",
.sta_mask = BIT(29),
.ctl_offs = 0x3AC,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_DIP] = {
.name = "dip",
.sta_mask = BIT(30),
.ctl_offs = 0x3B0,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_IPE] = {
.name = "ipe",
.sta_mask = BIT(31),
.ctl_offs = 0x3B4,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM] = {
.name = "cam",
.sta_mask = BIT(25),
.ctl_offs = 0x39C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.bp_infracfg = {
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
MT8195_TOP_AXI_PROT_EN_1_SET,
MT8195_TOP_AXI_PROT_EN_1_CLR,
MT8195_TOP_AXI_PROT_EN_1_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_RAWA] = {
.name = "cam_rawa",
.sta_mask = BIT(26),
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_RAWB] = {
.name = "cam_rawb",
.sta_mask = BIT(27),
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_MRAW] = {
.name = "cam_mraw",
.sta_mask = BIT(28),
.ctl_offs = 0x3A8,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
};
static const struct scpsys_soc_data mt8195_scpsys_data = {
.domains_data = scpsys_domain_data_mt8195,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195),
};
#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */

19
drivers/soc/mediatek/mtk-infracfg.c
View File

@ -6,6 +6,7 @@
#include <linux/export.h>
#include <linux/jiffies.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/soc/mediatek/infracfg.h>
#include <asm/processor.h>
@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
return ret;
}
static int __init mtk_infracfg_init(void)
{
struct regmap *infracfg;
/*
* MT8192 has an experimental path to route GPU traffic to the DSU's
* Accelerator Coherency Port, which is inadvertently enabled by
* default. It turns out not to work, so disable it to prevent spurious
* GPU faults.
*/
infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg");
if (!IS_ERR(infracfg))
regmap_set_bits(infracfg, MT8192_INFRA_CTRL,
MT8192_INFRA_CTRL_DISABLE_MFG2ACP);
return 0;
}
postcore_initcall(mtk_infracfg_init);

12
drivers/soc/mediatek/mtk-mmsys.c
View File

@ -15,6 +15,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
@ -56,6 +57,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@ -242,6 +250,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
{
.compatible = "mediatek,mt8186-mmsys",
.data = &mt8186_mmsys_driver_data,
},
{
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,

45
drivers/soc/mediatek/mtk-mutex.c
View File

@ -26,6 +26,23 @@
#define INT_MUTEX BIT(1)
#define MT8186_MUTEX_MOD_DISP_OVL0 0
#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
#define MT8186_MUTEX_MOD_DISP_RDMA0 2
#define MT8186_MUTEX_MOD_DISP_COLOR0 4
#define MT8186_MUTEX_MOD_DISP_CCORR0 5
#define MT8186_MUTEX_MOD_DISP_AAL0 7
#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
#define MT8186_MUTEX_MOD_DISP_DITHER0 10
#define MT8186_MUTEX_MOD_DISP_RDMA1 17
#define MT8186_MUTEX_SOF_SINGLE_MODE 0
#define MT8186_MUTEX_SOF_DSI0 1
#define MT8186_MUTEX_SOF_DPI0 2
#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
#define MT8167_MUTEX_MOD_DISP_PWM 1
#define MT8167_MUTEX_MOD_DISP_OVL0 6
#define MT8167_MUTEX_MOD_DISP_OVL1 7
@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
[DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
[DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
};
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
static const struct mtk_mutex_data mt8186_mutex_driver_data = {
.mutex_mod = mt8186_mutex_mod,
.mutex_sof = mt8186_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_mod = mt8192_mutex_mod,
.mutex_sof = mt8183_mutex_sof,
@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
{ .compatible = "mediatek,mt8186-disp-mutex",
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
{},

17
drivers/soc/mediatek/mtk-pm-domains.c
View File

@ -19,7 +19,9 @@
#include "mt8167-pm-domains.h"
#include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h"
#include "mt8186-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@ -60,10 +62,10 @@ static bool scpsys_domain_is_on(struct scpsys_domain *pd)
struct scpsys *scpsys = pd->scpsys;
u32 status, status2;
regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status);
regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status);
status &= pd->data->sta_mask;
regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2);
regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2);
status2 &= pd->data->sta_mask;
/* A domain is on when both status bits are set. */
@ -443,6 +445,9 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
pd->genpd.power_off = scpsys_power_off;
pd->genpd.power_on = scpsys_power_on;
if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP))
pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
pm_genpd_init(&pd->genpd, NULL, true);
else
@ -562,10 +567,18 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8183-power-controller",
.data = &mt8183_scpsys_data,
},
{
.compatible = "mediatek,mt8186-power-controller",
.data = &mt8186_scpsys_data,
},
{
.compatible = "mediatek,mt8192-power-controller",
.data = &mt8192_scpsys_data,
},
{
.compatible = "mediatek,mt8195-power-controller",
.data = &mt8195_scpsys_data,
},
{ }
};

8
drivers/soc/mediatek/mtk-pm-domains.h
View File

@ -37,7 +37,7 @@
#define PWR_STATUS_AUDIO BIT(24)
#define PWR_STATUS_USB BIT(25)
#define SPM_MAX_BUS_PROT_DATA 5
#define SPM_MAX_BUS_PROT_DATA 6
#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
.bus_prot_mask = (_mask), \
@ -72,8 +72,6 @@ struct scpsys_bus_prot_data {
bool ignore_clr_ack;
};
#define MAX_SUBSYS_CLKS 10
/**
* struct scpsys_domain_data - scp domain data for power on/off flow
* @name: The name of the power domain.
@ -94,13 +92,13 @@ struct scpsys_domain_data {
u8 caps;
const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
int pwr_sta_offs;
int pwr_sta2nd_offs;
};
struct scpsys_soc_data {
const struct scpsys_domain_data *domains_data;
int num_domains;
int pwr_sta_offs;
int pwr_sta2nd_offs;
};
#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */

71
drivers/soc/mediatek/mtk-pmic-wrap.c
View File

@ -30,6 +30,7 @@
#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
#define PWRAP_STATE_SYNC_IDLE0 BIT(20)
#define PWRAP_STATE_INIT_DONE0 BIT(21)
#define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22)
#define PWRAP_STATE_INIT_DONE1 BIT(15)
/* macro for WACS FSM */
@ -77,6 +78,7 @@
#define PWRAP_CAP_INT1_EN BIT(3)
#define PWRAP_CAP_WDT_SRC1 BIT(4)
#define PWRAP_CAP_ARB BIT(5)
#define PWRAP_CAP_ARB_MT8186 BIT(8)
/* defines for slave device wrapper registers */
enum dew_regs {
@ -1063,6 +1065,55 @@ static int mt8516_regs[] = {
[PWRAP_MSB_FIRST] = 0x170,
};
static int mt8186_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_RDDMY] = 0x20,
[PWRAP_CSHEXT_WRITE] = 0x24,
[PWRAP_CSHEXT_READ] = 0x28,
[PWRAP_CSLEXT_WRITE] = 0x2C,
[PWRAP_CSLEXT_READ] = 0x30,
[PWRAP_EXT_CK_WRITE] = 0x34,
[PWRAP_STAUPD_CTRL] = 0x3C,
[PWRAP_STAUPD_GRPEN] = 0x40,
[PWRAP_EINT_STA0_ADR] = 0x44,
[PWRAP_EINT_STA1_ADR] = 0x48,
[PWRAP_INT_CLR] = 0xC8,
[PWRAP_INT_FLG] = 0xC4,
[PWRAP_MAN_EN] = 0x7C,
[PWRAP_MAN_CMD] = 0x80,
[PWRAP_WACS0_EN] = 0x8C,
[PWRAP_WACS1_EN] = 0x94,
[PWRAP_WACS2_EN] = 0x9C,
[PWRAP_INIT_DONE0] = 0x90,
[PWRAP_INIT_DONE1] = 0x98,
[PWRAP_INIT_DONE2] = 0xA0,
[PWRAP_INT_EN] = 0xBC,
[PWRAP_INT1_EN] = 0xCC,
[PWRAP_INT1_FLG] = 0xD4,
[PWRAP_INT1_CLR] = 0xD8,
[PWRAP_TIMER_EN] = 0xF0,
[PWRAP_WDT_UNIT] = 0xF8,
[PWRAP_WDT_SRC_EN] = 0xFC,
[PWRAP_WDT_SRC_EN_1] = 0x100,
[PWRAP_WDT_FLG] = 0x104,
[PWRAP_SPMINF_STA] = 0x1B4,
[PWRAP_DCM_EN] = 0x1EC,
[PWRAP_DCM_DBC_PRD] = 0x1F0,
[PWRAP_GPSINF_0_STA] = 0x204,
[PWRAP_GPSINF_1_STA] = 0x208,
[PWRAP_WACS0_CMD] = 0xC00,
[PWRAP_WACS0_RDATA] = 0xC04,
[PWRAP_WACS0_VLDCLR] = 0xC08,
[PWRAP_WACS1_CMD] = 0xC10,
[PWRAP_WACS1_RDATA] = 0xC14,
[PWRAP_WACS1_VLDCLR] = 0xC18,
[PWRAP_WACS2_CMD] = 0xC20,
[PWRAP_WACS2_RDATA] = 0xC24,
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
enum pmic_type {
PMIC_MT6323,
PMIC_MT6351,
@ -1083,6 +1134,7 @@ enum pwrap_type {
PWRAP_MT8135,
PWRAP_MT8173,
PWRAP_MT8183,
PWRAP_MT8186,
PWRAP_MT8195,
PWRAP_MT8516,
};
@ -1535,6 +1587,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
case PWRAP_MT6779:
case PWRAP_MT6797:
case PWRAP_MT8173:
case PWRAP_MT8186:
case PWRAP_MT8516:
pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
break;
@ -2069,6 +2122,19 @@ static struct pmic_wrapper_type pwrap_mt8516 = {
.init_soc_specific = NULL,
};
static struct pmic_wrapper_type pwrap_mt8186 = {
.regs = mt8186_regs,
.type = PWRAP_MT8186,
.arb_en_all = 0xfb27f,
.int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */
.int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
static const struct of_device_id of_pwrap_match_tbl[] = {
{
.compatible = "mediatek,mt2701-pwrap",
@ -2097,6 +2163,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
}, {
.compatible = "mediatek,mt8183-pwrap",
.data = &pwrap_mt8183,
}, {
.compatible = "mediatek,mt8186-pwrap",
.data = &pwrap_mt8186,
}, {
.compatible = "mediatek,mt8195-pwrap",
.data = &pwrap_mt8195,
@ -2209,6 +2278,8 @@ static int pwrap_probe(struct platform_device *pdev)
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
mask_done = PWRAP_STATE_INIT_DONE1;
else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
mask_done = PWRAP_STATE_INIT_DONE0_MT8186;
else
mask_done = PWRAP_STATE_INIT_DONE0;

32
include/dt-bindings/power/mt8186-power.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H
#define _DT_BINDINGS_POWER_MT8186_POWER_H
#define MT8186_POWER_DOMAIN_MFG0 0
#define MT8186_POWER_DOMAIN_MFG1 1
#define MT8186_POWER_DOMAIN_MFG2 2
#define MT8186_POWER_DOMAIN_MFG3 3
#define MT8186_POWER_DOMAIN_SSUSB 4
#define MT8186_POWER_DOMAIN_SSUSB_P1 5
#define MT8186_POWER_DOMAIN_DIS 6
#define MT8186_POWER_DOMAIN_IMG 7
#define MT8186_POWER_DOMAIN_IMG2 8
#define MT8186_POWER_DOMAIN_IPE 9
#define MT8186_POWER_DOMAIN_CAM 10
#define MT8186_POWER_DOMAIN_CAM_RAWA 11
#define MT8186_POWER_DOMAIN_CAM_RAWB 12
#define MT8186_POWER_DOMAIN_VENC 13
#define MT8186_POWER_DOMAIN_VDEC 14
#define MT8186_POWER_DOMAIN_WPE 15
#define MT8186_POWER_DOMAIN_CONN_ON 16
#define MT8186_POWER_DOMAIN_CSIRX_TOP 17
#define MT8186_POWER_DOMAIN_ADSP_AO 18
#define MT8186_POWER_DOMAIN_ADSP_INFRA 19
#define MT8186_POWER_DOMAIN_ADSP_TOP 20
#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */

46
include/dt-bindings/power/mt8195-power.h Normal file
View File

@ -0,0 +1,46 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
#define _DT_BINDINGS_POWER_MT8195_POWER_H
#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0
#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1
#define MT8195_POWER_DOMAIN_PCIE_PHY 2
#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3
#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4
#define MT8195_POWER_DOMAIN_ETHER 5
#define MT8195_POWER_DOMAIN_ADSP 6
#define MT8195_POWER_DOMAIN_AUDIO 7
#define MT8195_POWER_DOMAIN_MFG0 8
#define MT8195_POWER_DOMAIN_MFG1 9
#define MT8195_POWER_DOMAIN_MFG2 10
#define MT8195_POWER_DOMAIN_MFG3 11
#define MT8195_POWER_DOMAIN_MFG4 12
#define MT8195_POWER_DOMAIN_MFG5 13
#define MT8195_POWER_DOMAIN_MFG6 14
#define MT8195_POWER_DOMAIN_VPPSYS0 15
#define MT8195_POWER_DOMAIN_VDOSYS0 16
#define MT8195_POWER_DOMAIN_VPPSYS1 17
#define MT8195_POWER_DOMAIN_VDOSYS1 18
#define MT8195_POWER_DOMAIN_DP_TX 19
#define MT8195_POWER_DOMAIN_EPD_TX 20
#define MT8195_POWER_DOMAIN_HDMI_TX 21
#define MT8195_POWER_DOMAIN_WPESYS 22
#define MT8195_POWER_DOMAIN_VDEC0 23
#define MT8195_POWER_DOMAIN_VDEC1 24
#define MT8195_POWER_DOMAIN_VDEC2 25
#define MT8195_POWER_DOMAIN_VENC 26
#define MT8195_POWER_DOMAIN_VENC_CORE1 27
#define MT8195_POWER_DOMAIN_IMG 28
#define MT8195_POWER_DOMAIN_DIP 29
#define MT8195_POWER_DOMAIN_IPE 30
#define MT8195_POWER_DOMAIN_CAM 31
#define MT8195_POWER_DOMAIN_CAM_RAWA 32
#define MT8195_POWER_DOMAIN_CAM_RAWB 33
#define MT8195_POWER_DOMAIN_CAM_MRAW 34
#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */

133
include/linux/soc/mediatek/infracfg.h
View File

@ -2,6 +2,88 @@
#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H
#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1)
#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3)
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)
#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11))
#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12))
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13)
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14)
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22)
#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23)
#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24)
#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25)
#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26)
#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27)
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28)
#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29)
#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15))
#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17))
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))
#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13)
#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14)
#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21)
#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22)
#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1)
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2)
#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28))
#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29))
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13)
#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14)
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19))
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20)
#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21)
#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
@ -58,6 +140,54 @@
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
/* MFG1 */
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
/* DIS */
#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
/* IMG */
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
/* IPE */
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
/* CAM */
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
/* VENC */
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
/* VDEC */
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
/* WPE */
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
/* CONN_ON */
#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
/* ADSP_TOP */
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
@ -147,6 +277,9 @@
#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
#define MT8192_INFRA_CTRL 0x290
#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9)
#define REG_INFRA_MISC 0xf00
#define F_DDR_4GB_SUPPORT_EN BIT(13)