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drm/amdgpu: give different sizes for each SA pool type
The IMMEDIATE (page fault) and DIRECT (reset) pool should be used only very rarely and by a single thread. Saves roughly 1.25MiB of memory and GART space for each amdgpu device. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -351,6 +351,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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*/
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int amdgpu_ib_pool_init(struct amdgpu_device *adev)
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{
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const int sizes[AMDGPU_IB_POOL_MAX] = {
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[AMDGPU_IB_POOL_DELAYED] = SZ_1M,
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[AMDGPU_IB_POOL_IMMEDIATE] = SZ_128K,
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[AMDGPU_IB_POOL_DIRECT] = SZ_512K
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};
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int r, i;
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if (adev->ib_pool_ready)
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@ -358,7 +363,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
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for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
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r = amdgpu_sa_bo_manager_init(adev, &adev->ib_pools[i],
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AMDGPU_IB_POOL_SIZE, 256,
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sizes[i], 256,
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AMDGPU_GEM_DOMAIN_GTT);
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if (r)
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goto error;
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@ -68,8 +68,6 @@ enum amdgpu_ring_priority_level {
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#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
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#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
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enum amdgpu_ring_type {
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AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
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AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
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