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dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format

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Convert fsl,vf610-mscm-ir.txt to yaml format.

Additional changes:
- remove label at example dts.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250724190342.1321632-1-Frank.Li@nxp.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Frank Li 2025-07-24 15:03:41 -04:00 committed by Rob Herring (Arm)
parent fa8c0b1c79
commit 1693d18772
2 changed files with 63 additions and 30 deletions
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30
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
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Freescale Vybrid Miscellaneous System Control - Interrupt Router
The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).
Required properties:
- compatible: "fsl,vf610-mscm-ir"
- reg: the register range of the MSCM Interrupt Router
- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
to get the current CPU ID
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Two cells, interrupt number and cells.
The hardware interrupt number according to interrupt
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
Example:
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
}

63
Documentation/devicetree/bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Vybrid Miscellaneous System Control - Interrupt Router
description:
The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,vf610-mscm-ir
reg:
maxItems: 1
fsl,cpucfg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The handle to the MSCM CPU configuration node, required
to get the current CPU ID
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
Two cells, interrupt number and cells.
The hardware interrupt number according to interrupt
assignment of the interrupt router is required.
Flags get passed only when using GIC as parent. Flags
encoding as documented by the GIC bindings.
required:
- compatible
- reg
- fsl,cpucfg
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
};